diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gv100/nvlink_gv100.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/nvlink_gv100.c | 25 |
1 files changed, 15 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c index e85b5a93..c328dd70 100644 --- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c +++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c | |||
@@ -1625,23 +1625,28 @@ static int gv100_nvlink_enable_links_pre_top(struct gk20a *g, u32 links) | |||
1625 | return -EINVAL; | 1625 | return -EINVAL; |
1626 | } | 1626 | } |
1627 | 1627 | ||
1628 | void gv100_nvlink_set_sw_war(struct gk20a *g, u32 link_id) | ||
1629 | { | ||
1630 | u32 reg; | ||
1631 | |||
1632 | /* WAR for HW bug 1888034 */ | ||
1633 | reg = DLPL_REG_RD32(g, link_id, nvl_sl0_safe_ctrl2_tx_r()); | ||
1634 | reg = set_field(reg, nvl_sl0_safe_ctrl2_tx_ctr_init_m(), | ||
1635 | nvl_sl0_safe_ctrl2_tx_ctr_init_init_f()); | ||
1636 | reg = set_field(reg, nvl_sl0_safe_ctrl2_tx_ctr_initscl_m(), | ||
1637 | nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_f()); | ||
1638 | DLPL_REG_WR32(g, link_id, nvl_sl0_safe_ctrl2_tx_r(), reg); | ||
1639 | } | ||
1640 | |||
1628 | static int gv100_nvlink_enable_links_post_top(struct gk20a *g, u32 links) | 1641 | static int gv100_nvlink_enable_links_post_top(struct gk20a *g, u32 links) |
1629 | { | 1642 | { |
1630 | u32 link_id; | 1643 | u32 link_id; |
1631 | unsigned long enabled_links = (links & g->nvlink.enabled_links) & | 1644 | unsigned long enabled_links = (links & g->nvlink.enabled_links) & |
1632 | ~g->nvlink.initialized_links; | 1645 | ~g->nvlink.initialized_links; |
1633 | u32 reg; | ||
1634 | 1646 | ||
1635 | for_each_set_bit(link_id, &enabled_links, 32) { | 1647 | for_each_set_bit(link_id, &enabled_links, 32) { |
1636 | 1648 | if (g->ops.nvlink.set_sw_war) | |
1637 | /* WAR for HW bug 1888034 */ | 1649 | g->ops.nvlink.set_sw_war(g, link_id); |
1638 | reg = DLPL_REG_RD32(g, link_id, nvl_sl0_safe_ctrl2_tx_r()); | ||
1639 | reg = set_field(reg, nvl_sl0_safe_ctrl2_tx_ctr_init_m(), | ||
1640 | nvl_sl0_safe_ctrl2_tx_ctr_init_init_f()); | ||
1641 | reg = set_field(reg, nvl_sl0_safe_ctrl2_tx_ctr_initscl_m(), | ||
1642 | nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_f()); | ||
1643 | DLPL_REG_WR32(g, link_id, nvl_sl0_safe_ctrl2_tx_r(), reg); | ||
1644 | |||
1645 | gv100_nvlink_initialize_tlc(g, link_id); | 1650 | gv100_nvlink_initialize_tlc(g, link_id); |
1646 | gv100_nvlink_initialize_nvlipt(g, link_id); | 1651 | gv100_nvlink_initialize_nvlipt(g, link_id); |
1647 | gv100_nvlink_enable_link_intr(g, link_id, true); | 1652 | gv100_nvlink_enable_link_intr(g, link_id, true); |