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path: root/drivers/gpu/nvgpu/gv100/mc_gv100.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gv100/mc_gv100.c')
-rw-r--r--drivers/gpu/nvgpu/gv100/mc_gv100.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gv100/mc_gv100.c b/drivers/gpu/nvgpu/gv100/mc_gv100.c
index 46af100a..7d38a3fb 100644
--- a/drivers/gpu/nvgpu/gv100/mc_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/mc_gv100.c
@@ -66,15 +66,14 @@ bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0)
66 return (((mc_intr_0 & mc_intr_nvlink_pending_f()) != 0U) ? true : false); 66 return (((mc_intr_0 & mc_intr_nvlink_pending_f()) != 0U) ? true : false);
67} 67}
68 68
69bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id) 69bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
70 u32 *eng_intr_pending)
70{ 71{
71 u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); 72 u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
72 u32 stall_intr, eng_intr_mask; 73 u32 stall_intr, eng_intr_mask;
73 74
74 eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id); 75 eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id);
75 if ((mc_intr_0 & eng_intr_mask) != 0U) { 76 *eng_intr_pending = mc_intr_0 & eng_intr_mask;
76 return true;
77 }
78 77
79 stall_intr = mc_intr_pfifo_pending_f() | 78 stall_intr = mc_intr_pfifo_pending_f() |
80 mc_intr_hub_pending_f() | 79 mc_intr_hub_pending_f() |
@@ -82,9 +81,10 @@ bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id)
82 mc_intr_pbus_pending_f() | 81 mc_intr_pbus_pending_f() |
83 mc_intr_ltc_pending_f() | 82 mc_intr_ltc_pending_f() |
84 mc_intr_nvlink_pending_f(); 83 mc_intr_nvlink_pending_f();
85 if ((mc_intr_0 & stall_intr) != 0U) {
86 return true;
87 }
88 84
89 return false; 85 nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr,
86 "mc_intr_0 = 0x%08x, eng_intr = 0x%08x",
87 mc_intr_0 & stall_intr, *eng_intr_pending);
88
89 return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U;
90} 90}