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path: root/drivers/gpu/nvgpu/gv100/mc_gv100.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gv100/mc_gv100.c')
-rw-r--r--drivers/gpu/nvgpu/gv100/mc_gv100.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gv100/mc_gv100.c b/drivers/gpu/nvgpu/gv100/mc_gv100.c
index 2d84a3a8..7ed9e6da 100644
--- a/drivers/gpu/nvgpu/gv100/mc_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/mc_gv100.c
@@ -72,14 +72,15 @@ bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0)
72 return (((mc_intr_0 & mc_intr_nvlink_pending_f()) != 0U) ? true : false); 72 return (((mc_intr_0 & mc_intr_nvlink_pending_f()) != 0U) ? true : false);
73} 73}
74 74
75bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, 75bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id)
76 u32 *eng_intr_pending)
77{ 76{
78 u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); 77 u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
79 u32 stall_intr, eng_intr_mask; 78 u32 stall_intr, eng_intr_mask;
80 79
81 eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id); 80 eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id);
82 *eng_intr_pending = mc_intr_0 & eng_intr_mask; 81 if ((mc_intr_0 & eng_intr_mask) != 0U) {
82 return true;
83 }
83 84
84 stall_intr = mc_intr_pfifo_pending_f() | 85 stall_intr = mc_intr_pfifo_pending_f() |
85 mc_intr_hub_pending_f() | 86 mc_intr_hub_pending_f() |
@@ -87,10 +88,9 @@ bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
87 mc_intr_pbus_pending_f() | 88 mc_intr_pbus_pending_f() |
88 mc_intr_ltc_pending_f() | 89 mc_intr_ltc_pending_f() |
89 mc_intr_nvlink_pending_f(); 90 mc_intr_nvlink_pending_f();
91 if ((mc_intr_0 & stall_intr) != 0U) {
92 return true;
93 }
90 94
91 nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr, 95 return false;
92 "mc_intr_0 = 0x%08x, eng_intr = 0x%08x",
93 mc_intr_0 & stall_intr, *eng_intr_pending);
94
95 return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U;
96} 96}