1 files changed, 94 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv100/mc_gv100.c b/drivers/gpu/nvgpu/gv100/mc_gv100.c
new file mode 100644
index 00000000..a3f8ab06
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv100/mc_gv100.c
@@ -0,0 +1,94 @@
+/*
+ * GV100 master
+ *
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <linux/types.h>
+
+#include "gk20a/gk20a.h"
+
+#include "gp10b/mc_gp10b.h"
+
+#include "mc_gv100.h"
+#include "gv11b/fb_gv11b.h"
+
+#include <nvgpu/hw/gv100/hw_mc_gv100.h>
+
+void mc_gv100_intr_enable(struct gk20a *g)
+{
+        u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
+
+        gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
+                                0xffffffff);
+        gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
+                                0xffffffff);
+        gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL);
+
+        g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
+                                mc_intr_pfifo_pending_f() |
+                                mc_intr_hub_pending_f() |
+                                mc_intr_priv_ring_pending_f() |
+                                mc_intr_pbus_pending_f() |
+                                mc_intr_ltc_pending_f() |
+                                mc_intr_nvlink_pending_f() |
+                                eng_intr_mask;
+
+        g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
+                                mc_intr_pfifo_pending_f()
+                             | eng_intr_mask;
+
+        /* TODO: Enable PRI faults for HUB ECC err intr */
+        gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, g->mm.hub_intr_types);
+
+        gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
+                        g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
+
+        gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
+                        g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
+
+}
+
+bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0)
+{
+        return ((mc_intr_0 & mc_intr_nvlink_pending_f()) ? true : false);
+}
+
+bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id)
+{
+        u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
+        u32 stall_intr, eng_intr_mask;
+
+        eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id);
+        if (mc_intr_0 & eng_intr_mask)
+                return true;
+
+        stall_intr = mc_intr_pfifo_pending_f() |
+                        mc_intr_hub_pending_f() |
+                        mc_intr_priv_ring_pending_f() |
+                        mc_intr_pbus_pending_f() |
+                        mc_intr_ltc_pending_f() |
+                        mc_intr_nvlink_pending_f();
+        if (mc_intr_0 & stall_intr)
+                return true;
+
+        return false;
+}