summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gv100/hal_gv100.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/nvgpu/gv100/hal_gv100.c')
-rw-r--r--drivers/gpu/nvgpu/gv100/hal_gv100.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index f20d2dcf..cefaf1ae 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -78,7 +78,7 @@
78 78
79#include "gv11b/dbg_gpu_gv11b.h" 79#include "gv11b/dbg_gpu_gv11b.h"
80#include "gv11b/hal_gv11b.h" 80#include "gv11b/hal_gv11b.h"
81#include "gv11b/gr_gv11b.h" 81#include "gv100/gr_gv100.h"
82#include "gv11b/mc_gv11b.h" 82#include "gv11b/mc_gv11b.h"
83#include "gv11b/ltc_gv11b.h" 83#include "gv11b/ltc_gv11b.h"
84#include "gv11b/gv11b.h" 84#include "gv11b/gv11b.h"
@@ -263,8 +263,8 @@ static const struct gpu_ops gv100_ops = {
263 }, 263 },
264 .gr = { 264 .gr = {
265 .init_gpc_mmu = gr_gv11b_init_gpc_mmu, 265 .init_gpc_mmu = gr_gv11b_init_gpc_mmu,
266 .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults, 266 .bundle_cb_defaults = gr_gv100_bundle_cb_defaults,
267 .cb_size_default = gr_gv11b_cb_size_default, 267 .cb_size_default = gr_gv100_cb_size_default,
268 .calc_global_ctx_buffer_size = 268 .calc_global_ctx_buffer_size =
269 gr_gv11b_calc_global_ctx_buffer_size, 269 gr_gv11b_calc_global_ctx_buffer_size,
270 .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb, 270 .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb,
@@ -285,7 +285,7 @@ static const struct gpu_ops gv100_ops = {
285 .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, 285 .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask,
286 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, 286 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
287 .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode, 287 .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode,
288 .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask, 288 .set_gpc_tpc_mask = gr_gv100_set_gpc_tpc_mask,
289 .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, 289 .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask,
290 .free_channel_ctx = gk20a_free_channel_ctx, 290 .free_channel_ctx = gk20a_free_channel_ctx,
291 .alloc_obj_ctx = gk20a_alloc_obj_ctx, 291 .alloc_obj_ctx = gk20a_alloc_obj_ctx,
@@ -335,7 +335,7 @@ static const struct gpu_ops gv100_ops = {
335 .resume_contexts = gr_gk20a_resume_contexts, 335 .resume_contexts = gr_gk20a_resume_contexts,
336 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, 336 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
337 .fuse_override = gp10b_gr_fuse_override, 337 .fuse_override = gp10b_gr_fuse_override,
338 .init_sm_id_table = gr_gv11b_init_sm_id_table, 338 .init_sm_id_table = gr_gv100_init_sm_id_table,
339 .load_smid_config = gr_gv11b_load_smid_config, 339 .load_smid_config = gr_gv11b_load_smid_config,
340 .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, 340 .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering,
341 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, 341 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,