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Diffstat (limited to 'drivers/gpu/nvgpu/gv100/hal_gv100.c')
-rw-r--r--drivers/gpu/nvgpu/gv100/hal_gv100.c441
1 files changed, 441 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
new file mode 100644
index 00000000..337c607f
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -0,0 +1,441 @@
1/*
2 * GV100 Tegra HAL interface
3 *
4 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/types.h>
17#include <linux/printk.h>
18
19#include <linux/types.h>
20#include <linux/tegra_gpu_t19x.h>
21
22#include "gk20a/gk20a.h"
23#include "gk20a/fifo_gk20a.h"
24#include "gk20a/ctxsw_trace_gk20a.h"
25#include "gk20a/fecs_trace_gk20a.h"
26#include "gk20a/css_gr_gk20a.h"
27#include "gk20a/mc_gk20a.h"
28#include "gk20a/dbg_gpu_gk20a.h"
29#include "gk20a/bus_gk20a.h"
30#include "gk20a/pramin_gk20a.h"
31#include "gk20a/flcn_gk20a.h"
32#include "gk20a/regops_gk20a.h"
33
34#include "gm20b/ltc_gm20b.h"
35#include "gm20b/gr_gm20b.h"
36#include "gm20b/fifo_gm20b.h"
37
38#include "gp106/clk_gp106.h"
39#include "gp106/clk_arb_gp106.h"
40#include "gp106/pmu_gp106.h"
41
42#include "gm206/bios_gm206.h"
43#include "gp106/therm_gp106.h"
44#include "gp106/xve_gp106.h"
45#include "gp106/clk_gp106.h"
46#include "gp106/flcn_gp106.h"
47#include "gp10b/ltc_gp10b.h"
48#include "gp10b/therm_gp10b.h"
49#include "gp10b/mc_gp10b.h"
50#include "gp10b/ce_gp10b.h"
51#include "gp10b/priv_ring_gp10b.h"
52#include "gp10b/fifo_gp10b.h"
53#include "gp10b/fecs_trace_gp10b.h"
54
55#include "gv11b/hal_gv11b.h"
56#include "gv11b/gr_gv11b.h"
57#include "gv11b/mc_gv11b.h"
58#include "gv11b/ltc_gv11b.h"
59#include "gv11b/gv11b.h"
60#include "gv11b/ce_gv11b.h"
61#include "gv100/gr_ctx_gv100.h"
62#include "gv100/mm_gv100.h"
63#include "gv11b/pmu_gv11b.h"
64#include "gv100/fb_gv100.h"
65#include "gv11b/fifo_gv11b.h"
66#include "gv11b/gv11b_gating_reglist.h"
67#include "gv11b/regops_gv11b.h"
68#include "gv11b/subctx_gv11b.h"
69
70#include "gv100.h"
71#include "hal_gv100.h"
72
73#include <nvgpu/debug.h>
74#include <nvgpu/enabled.h>
75
76#include <nvgpu/hw/gv100/hw_proj_gv100.h>
77#include <nvgpu/hw/gv100/hw_fifo_gv100.h>
78#include <nvgpu/hw/gv100/hw_ram_gv100.h>
79#include <nvgpu/hw/gv100/hw_top_gv100.h>
80#include <nvgpu/hw/gv100/hw_pram_gv100.h>
81
82static int gv100_get_litter_value(struct gk20a *g, int value)
83{
84 int ret = EINVAL;
85 switch (value) {
86 case GPU_LIT_NUM_GPCS:
87 ret = proj_scal_litter_num_gpcs_v();
88 break;
89 case GPU_LIT_NUM_PES_PER_GPC:
90 ret = proj_scal_litter_num_pes_per_gpc_v();
91 break;
92 case GPU_LIT_NUM_ZCULL_BANKS:
93 ret = proj_scal_litter_num_zcull_banks_v();
94 break;
95 case GPU_LIT_NUM_TPC_PER_GPC:
96 ret = proj_scal_litter_num_tpc_per_gpc_v();
97 break;
98 case GPU_LIT_NUM_SM_PER_TPC:
99 ret = proj_scal_litter_num_sm_per_tpc_v();
100 break;
101 case GPU_LIT_NUM_FBPS:
102 ret = proj_scal_litter_num_fbps_v();
103 break;
104 case GPU_LIT_GPC_BASE:
105 ret = proj_gpc_base_v();
106 break;
107 case GPU_LIT_GPC_STRIDE:
108 ret = proj_gpc_stride_v();
109 break;
110 case GPU_LIT_GPC_SHARED_BASE:
111 ret = proj_gpc_shared_base_v();
112 break;
113 case GPU_LIT_TPC_IN_GPC_BASE:
114 ret = proj_tpc_in_gpc_base_v();
115 break;
116 case GPU_LIT_TPC_IN_GPC_STRIDE:
117 ret = proj_tpc_in_gpc_stride_v();
118 break;
119 case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
120 ret = proj_tpc_in_gpc_shared_base_v();
121 break;
122 case GPU_LIT_PPC_IN_GPC_BASE:
123 ret = proj_ppc_in_gpc_base_v();
124 case GPU_LIT_PPC_IN_GPC_STRIDE:
125 ret = proj_ppc_in_gpc_stride_v();
126 break;
127 case GPU_LIT_ROP_BASE:
128 ret = proj_rop_base_v();
129 break;
130 case GPU_LIT_ROP_STRIDE:
131 ret = proj_rop_stride_v();
132 break;
133 case GPU_LIT_ROP_SHARED_BASE:
134 ret = proj_rop_shared_base_v();
135 break;
136 case GPU_LIT_HOST_NUM_ENGINES:
137 ret = proj_host_num_engines_v();
138 break;
139 case GPU_LIT_HOST_NUM_PBDMA:
140 ret = proj_host_num_pbdma_v();
141 break;
142 case GPU_LIT_LTC_STRIDE:
143 ret = proj_ltc_stride_v();
144 break;
145 case GPU_LIT_LTS_STRIDE:
146 ret = proj_lts_stride_v();
147 break;
148 case GPU_LIT_NUM_FBPAS:
149 ret = proj_scal_litter_num_fbpas_v();
150 break;
151 case GPU_LIT_FBPA_STRIDE:
152 ret = proj_fbpa_stride_v();
153 break;
154 case GPU_LIT_SM_PRI_STRIDE:
155 ret = proj_sm_stride_v();
156 break;
157
158 default:
159 break;
160 }
161
162 return ret;
163}
164
165int gv100_init_gpu_characteristics(struct gk20a *g)
166{
167 struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics;
168
169 int err;
170
171 err = gk20a_init_gpu_characteristics(g);
172 if (err)
173 return err;
174
175 gpu->flags |=
176 NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS;
177
178 return 0;
179}
180
181
182
183static const struct gpu_ops gv100_ops = {
184 .ltc = {
185 .determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
186 .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry,
187 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
188 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
189 .init_cbc = NULL,
190 .init_fs_state = gv11b_ltc_init_fs_state,
191 .init_comptags = gp10b_ltc_init_comptags,
192 .cbc_ctrl = gm20b_ltc_cbc_ctrl,
193 .isr = gv11b_ltc_isr,
194 .cbc_fix_config = gv11b_ltc_cbc_fix_config,
195 .flush = gm20b_flush_ltc,
196 .set_enabled = gp10b_ltc_set_enabled,
197 },
198 .ce2 = {
199 .isr_stall = gv11b_ce_isr,
200 .isr_nonstall = gp10b_ce_nonstall_isr,
201 .get_num_pce = gv11b_ce_get_num_pce,
202 },
203 .fifo = {
204 .init_fifo_setup_hw = gv11b_init_fifo_setup_hw,
205 .bind_channel = channel_gm20b_bind,
206 .unbind_channel = channel_gv11b_unbind,
207 .disable_channel = gk20a_fifo_disable_channel,
208 .enable_channel = gk20a_fifo_enable_channel,
209 .alloc_inst = gk20a_fifo_alloc_inst,
210 .free_inst = gk20a_fifo_free_inst,
211 .setup_ramfc = channel_gv11b_setup_ramfc,
212 .channel_set_priority = gk20a_fifo_set_priority,
213 .channel_set_timeslice = gk20a_fifo_set_timeslice,
214 .default_timeslice_us = gk20a_fifo_default_timeslice_us,
215 .setup_userd = gk20a_fifo_setup_userd,
216 .userd_gp_get = gv11b_userd_gp_get,
217 .userd_gp_put = gv11b_userd_gp_put,
218 .userd_pb_get = gv11b_userd_pb_get,
219 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
220 .preempt_channel = gv11b_fifo_preempt_channel,
221 .preempt_tsg = gv11b_fifo_preempt_tsg,
222 .update_runlist = gk20a_fifo_update_runlist,
223 .trigger_mmu_fault = NULL,
224 .get_mmu_fault_info = NULL,
225 .wait_engine_idle = gk20a_fifo_wait_engine_idle,
226 .get_num_fifos = gv11b_fifo_get_num_fifos,
227 .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
228 .set_runlist_interleave = gk20a_fifo_set_runlist_interleave,
229 .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
230 .force_reset_ch = gk20a_fifo_force_reset_ch,
231 .engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
232 .device_info_data_parse = gp10b_device_info_data_parse,
233 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
234 .init_engine_info = gk20a_fifo_init_engine_info,
235 .runlist_entry_size = ram_rl_entry_size_v,
236 .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry,
237 .get_ch_runlist_entry = gv11b_get_ch_runlist_entry,
238 .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
239 .dump_pbdma_status = gk20a_dump_pbdma_status,
240 .dump_eng_status = gv11b_dump_eng_status,
241 .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
242 .intr_0_error_mask = gv11b_fifo_intr_0_error_mask,
243 .is_preempt_pending = gv11b_fifo_is_preempt_pending,
244 .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs,
245 .reset_enable_hw = gv11b_init_fifo_reset_enable_hw,
246 .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg,
247 .handle_sched_error = gv11b_fifo_handle_sched_error,
248 .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0,
249 .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1,
250 .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers,
251 .deinit_eng_method_buffers =
252 gv11b_fifo_deinit_eng_method_buffers,
253 .tsg_bind_channel = gk20a_tsg_bind_channel,
254 .tsg_unbind_channel = gk20a_tsg_unbind_channel,
255#ifdef CONFIG_TEGRA_GK20A_NVHOST
256 .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf,
257 .free_syncpt_buf = gv11b_fifo_free_syncpt_buf,
258 .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd,
259 .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size,
260 .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd,
261 .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size,
262#endif
263 .resetup_ramfc = NULL,
264 .device_info_fault_id = top_device_info_data_fault_id_enum_v,
265 .free_channel_ctx_header = gv11b_free_subctx_header,
266 .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg,
267 .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout,
268 },
269 .gr_ctx = {
270 .get_netlist_name = gr_gv100_get_netlist_name,
271 .is_fw_defined = gr_gv100_is_firmware_defined,
272 },
273#ifdef CONFIG_GK20A_CTXSW_TRACE
274 .fecs_trace = {
275 .alloc_user_buffer = gk20a_ctxsw_dev_ring_alloc,
276 .free_user_buffer = gk20a_ctxsw_dev_ring_free,
277 .mmap_user_buffer = gk20a_ctxsw_dev_mmap_buffer,
278 .init = gk20a_fecs_trace_init,
279 .deinit = gk20a_fecs_trace_deinit,
280 .enable = gk20a_fecs_trace_enable,
281 .disable = gk20a_fecs_trace_disable,
282 .is_enabled = gk20a_fecs_trace_is_enabled,
283 .reset = gk20a_fecs_trace_reset,
284 .flush = gp10b_fecs_trace_flush,
285 .poll = gk20a_fecs_trace_poll,
286 .bind_channel = gk20a_fecs_trace_bind_channel,
287 .unbind_channel = gk20a_fecs_trace_unbind_channel,
288 .max_entries = gk20a_gr_max_entries,
289 },
290#endif /* CONFIG_GK20A_CTXSW_TRACE */
291 .pramin = {
292 .enter = gk20a_pramin_enter,
293 .exit = gk20a_pramin_exit,
294 .data032_r = pram_data032_r,
295 },
296 .clk = {
297 .init_clk_support = gp106_init_clk_support,
298 .get_crystal_clk_hz = gp106_crystal_clk_hz,
299 .measure_freq = gp106_clk_measure_freq,
300 .suspend_clk_support = gp106_suspend_clk_support,
301 },
302 .clk_arb = {
303 .get_arbiter_clk_domains = gp106_get_arbiter_clk_domains,
304 .get_arbiter_clk_range = gp106_get_arbiter_clk_range,
305 .get_arbiter_clk_default = gp106_get_arbiter_clk_default,
306 .get_current_pstate = nvgpu_clk_arb_get_current_pstate,
307 },
308 .mc = {
309 .intr_enable = mc_gv11b_intr_enable,
310 .intr_unit_config = mc_gp10b_intr_unit_config,
311 .isr_stall = mc_gp10b_isr_stall,
312 .intr_stall = mc_gp10b_intr_stall,
313 .intr_stall_pause = mc_gp10b_intr_stall_pause,
314 .intr_stall_resume = mc_gp10b_intr_stall_resume,
315 .intr_nonstall = mc_gp10b_intr_nonstall,
316 .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
317 .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
318 .enable = gk20a_mc_enable,
319 .disable = gk20a_mc_disable,
320 .reset = gk20a_mc_reset,
321 .boot_0 = gk20a_mc_boot_0,
322 .is_intr1_pending = mc_gp10b_is_intr1_pending,
323 .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending,
324 },
325 .debug = {
326 .show_dump = gk20a_debug_show_dump,
327 },
328 .dbg_session_ops = {
329 .exec_reg_ops = exec_regops_gk20a,
330 .dbg_set_powergate = dbg_set_powergate,
331 .check_and_set_global_reservation =
332 nvgpu_check_and_set_global_reservation,
333 .check_and_set_context_reservation =
334 nvgpu_check_and_set_context_reservation,
335 .release_profiler_reservation =
336 nvgpu_release_profiler_reservation,
337 .perfbuffer_enable = gk20a_perfbuf_enable_locked,
338 .perfbuffer_disable = gk20a_perfbuf_disable_locked,
339 },
340 .bus = {
341 .init_hw = gk20a_bus_init_hw,
342 .isr = gk20a_bus_isr,
343 .read_ptimer = gk20a_read_ptimer,
344 .bar1_bind = NULL,
345 },
346#if defined(CONFIG_GK20A_CYCLE_STATS)
347 .css = {
348 .enable_snapshot = css_hw_enable_snapshot,
349 .disable_snapshot = css_hw_disable_snapshot,
350 .check_data_available = css_hw_check_data_available,
351 .set_handled_snapshots = css_hw_set_handled_snapshots,
352 .allocate_perfmon_ids = css_gr_allocate_perfmon_ids,
353 .release_perfmon_ids = css_gr_release_perfmon_ids,
354 },
355#endif
356 .xve = {
357 .sw_init = xve_sw_init_gp106,
358 .get_speed = xve_get_speed_gp106,
359 .set_speed = xve_set_speed_gp106,
360 .available_speeds = xve_available_speeds_gp106,
361 .xve_readl = xve_xve_readl_gp106,
362 .xve_writel = xve_xve_writel_gp106,
363 .disable_aspm = xve_disable_aspm_gp106,
364 .reset_gpu = xve_reset_gpu_gp106,
365#if defined(CONFIG_PCI_MSI)
366 .rearm_msi = xve_rearm_msi_gp106,
367#endif
368 .enable_shadow_rom = xve_enable_shadow_rom_gp106,
369 .disable_shadow_rom = xve_disable_shadow_rom_gp106,
370 },
371 .falcon = {
372 .falcon_hal_sw_init = gp106_falcon_hal_sw_init,
373 },
374 .priv_ring = {
375 .isr = gp10b_priv_ring_isr,
376 },
377 .chip_init_gpu_characteristics = gv100_init_gpu_characteristics,
378 .get_litter_value = gv100_get_litter_value,
379 .bios_init = gm206_bios_init,
380};
381
382int gv100_init_hal(struct gk20a *g)
383{
384 struct gpu_ops *gops = &g->ops;
385 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
386
387 gops->ltc = gv100_ops.ltc;
388 gops->ce2 = gv100_ops.ce2;
389 gops->clock_gating = gv100_ops.clock_gating;
390 gops->fifo = gv100_ops.fifo;
391 gops->gr_ctx = gv100_ops.gr_ctx;
392 gops->fecs_trace = gv100_ops.fecs_trace;
393 gops->pramin = gv100_ops.pramin;
394 gops->therm = gv100_ops.therm;
395 gops->mc = gv100_ops.mc;
396 gops->debug = gv100_ops.debug;
397 gops->dbg_session_ops = gv100_ops.dbg_session_ops;
398 gops->bus = gv100_ops.bus;
399#if defined(CONFIG_GK20A_CYCLE_STATS)
400 gops->css = gv100_ops.css;
401#endif
402 gops->xve = gv100_ops.xve;
403 gops->falcon = gv100_ops.falcon;
404 gops->priv_ring = gv100_ops.priv_ring;
405
406 /* clocks */
407 gops->clk.init_clk_support = gv100_ops.clk.init_clk_support;
408 gops->clk.get_crystal_clk_hz = gv100_ops.clk.get_crystal_clk_hz;
409 gops->clk.measure_freq = gv100_ops.clk.measure_freq;
410 gops->clk.suspend_clk_support = gv100_ops.clk.suspend_clk_support;
411
412 /* Lone functions */
413 gops->chip_init_gpu_characteristics =
414 gv100_ops.chip_init_gpu_characteristics;
415 gops->get_litter_value = gv100_ops.get_litter_value;
416 gops->bios_init = gv100_ops.bios_init;
417
418 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
419 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
420 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
421 /* for now */
422 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
423
424 g->bootstrap_owner = LSF_FALCON_ID_SEC2;
425
426 gv11b_init_gr(g);
427 gv100_init_fb(gops);
428 gv100_init_mm(gops);
429 gp106_init_pmu_ops(g);
430
431 g->name = "gv10x";
432
433 c->twod_class = FERMI_TWOD_A;
434 c->threed_class = VOLTA_A;
435 c->compute_class = VOLTA_COMPUTE_A;
436 c->gpfifo_class = VOLTA_CHANNEL_GPFIFO_A;
437 c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
438 c->dma_copy_class = VOLTA_DMA_COPY_A;
439
440 return 0;
441}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 20:58:03 -0400