diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gv100/hal_gv100.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 769 |
1 files changed, 769 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c new file mode 100644 index 00000000..4044c4b5 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -0,0 +1,769 @@ | |||
1 | /* | ||
2 | * GV100 Tegra HAL interface | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <linux/types.h> | ||
26 | #include <linux/printk.h> | ||
27 | |||
28 | #include <linux/types.h> | ||
29 | #include <linux/tegra_gpu_t19x.h> | ||
30 | |||
31 | #include "gk20a/gk20a.h" | ||
32 | #include "gk20a/fifo_gk20a.h" | ||
33 | #include "gk20a/fecs_trace_gk20a.h" | ||
34 | #include "gk20a/css_gr_gk20a.h" | ||
35 | #include "gk20a/mc_gk20a.h" | ||
36 | #include "gk20a/dbg_gpu_gk20a.h" | ||
37 | #include "gk20a/bus_gk20a.h" | ||
38 | #include "gk20a/pramin_gk20a.h" | ||
39 | #include "gk20a/flcn_gk20a.h" | ||
40 | #include "gk20a/regops_gk20a.h" | ||
41 | #include "gk20a/fb_gk20a.h" | ||
42 | #include "gk20a/mm_gk20a.h" | ||
43 | #include "gk20a/pmu_gk20a.h" | ||
44 | #include "gk20a/gr_gk20a.h" | ||
45 | |||
46 | #include "gm20b/ltc_gm20b.h" | ||
47 | #include "gm20b/gr_gm20b.h" | ||
48 | #include "gm20b/fifo_gm20b.h" | ||
49 | #include "gm20b/fb_gm20b.h" | ||
50 | #include "gm20b/mm_gm20b.h" | ||
51 | #include "gm20b/pmu_gm20b.h" | ||
52 | #include "gm20b/acr_gm20b.h" | ||
53 | |||
54 | #include "gp10b/fb_gp10b.h" | ||
55 | #include "gp10b/gr_gp10b.h" | ||
56 | |||
57 | #include "gp106/clk_gp106.h" | ||
58 | #include "gp106/clk_arb_gp106.h" | ||
59 | #include "gp106/pmu_gp106.h" | ||
60 | #include "gp106/acr_gp106.h" | ||
61 | #include "gp106/sec2_gp106.h" | ||
62 | #include "gp106/bios_gp106.h" | ||
63 | #include "gv100/bios_gv100.h" | ||
64 | #include "gp106/therm_gp106.h" | ||
65 | #include "gp106/xve_gp106.h" | ||
66 | #include "gp106/clk_gp106.h" | ||
67 | #include "gp106/flcn_gp106.h" | ||
68 | #include "gp10b/ltc_gp10b.h" | ||
69 | #include "gp10b/therm_gp10b.h" | ||
70 | #include "gp10b/mc_gp10b.h" | ||
71 | #include "gp10b/ce_gp10b.h" | ||
72 | #include "gp10b/priv_ring_gp10b.h" | ||
73 | #include "gp10b/fifo_gp10b.h" | ||
74 | #include "gp10b/fecs_trace_gp10b.h" | ||
75 | #include "gp10b/mm_gp10b.h" | ||
76 | #include "gp10b/pmu_gp10b.h" | ||
77 | |||
78 | #include "gv11b/css_gr_gv11b.h" | ||
79 | #include "gv11b/dbg_gpu_gv11b.h" | ||
80 | #include "gv11b/hal_gv11b.h" | ||
81 | #include "gv100/gr_gv100.h" | ||
82 | #include "gv11b/mc_gv11b.h" | ||
83 | #include "gv11b/ltc_gv11b.h" | ||
84 | #include "gv11b/gv11b.h" | ||
85 | #include "gv11b/ce_gv11b.h" | ||
86 | #include "gv100/gr_ctx_gv100.h" | ||
87 | #include "gv11b/mm_gv11b.h" | ||
88 | #include "gv11b/pmu_gv11b.h" | ||
89 | #include "gv11b/fb_gv11b.h" | ||
90 | #include "gv100/mm_gv100.h" | ||
91 | #include "gv11b/pmu_gv11b.h" | ||
92 | #include "gv100/fb_gv100.h" | ||
93 | #include "gv100/fifo_gv100.h" | ||
94 | #include "gv11b/fifo_gv11b.h" | ||
95 | #include "gv11b/regops_gv11b.h" | ||
96 | |||
97 | #include "gv11b/gv11b_gating_reglist.h" | ||
98 | #include "gv100/regops_gv100.h" | ||
99 | #include "gv11b/subctx_gv11b.h" | ||
100 | |||
101 | #include "gv100.h" | ||
102 | #include "hal_gv100.h" | ||
103 | #include "gv100/fb_gv100.h" | ||
104 | #include "gv100/mm_gv100.h" | ||
105 | |||
106 | #include <nvgpu/bus.h> | ||
107 | #include <nvgpu/debug.h> | ||
108 | #include <nvgpu/enabled.h> | ||
109 | #include <nvgpu/enabled_t19x.h> | ||
110 | #include <nvgpu/ctxsw_trace.h> | ||
111 | |||
112 | #include <nvgpu/hw/gv100/hw_proj_gv100.h> | ||
113 | #include <nvgpu/hw/gv100/hw_fifo_gv100.h> | ||
114 | #include <nvgpu/hw/gv100/hw_ram_gv100.h> | ||
115 | #include <nvgpu/hw/gv100/hw_top_gv100.h> | ||
116 | #include <nvgpu/hw/gv100/hw_pram_gv100.h> | ||
117 | #include <nvgpu/hw/gv100/hw_pwr_gv100.h> | ||
118 | |||
119 | static int gv100_get_litter_value(struct gk20a *g, int value) | ||
120 | { | ||
121 | int ret = EINVAL; | ||
122 | switch (value) { | ||
123 | case GPU_LIT_NUM_GPCS: | ||
124 | ret = proj_scal_litter_num_gpcs_v(); | ||
125 | break; | ||
126 | case GPU_LIT_NUM_PES_PER_GPC: | ||
127 | ret = proj_scal_litter_num_pes_per_gpc_v(); | ||
128 | break; | ||
129 | case GPU_LIT_NUM_ZCULL_BANKS: | ||
130 | ret = proj_scal_litter_num_zcull_banks_v(); | ||
131 | break; | ||
132 | case GPU_LIT_NUM_TPC_PER_GPC: | ||
133 | ret = proj_scal_litter_num_tpc_per_gpc_v(); | ||
134 | break; | ||
135 | case GPU_LIT_NUM_SM_PER_TPC: | ||
136 | ret = proj_scal_litter_num_sm_per_tpc_v(); | ||
137 | break; | ||
138 | case GPU_LIT_NUM_FBPS: | ||
139 | ret = proj_scal_litter_num_fbps_v(); | ||
140 | break; | ||
141 | case GPU_LIT_GPC_BASE: | ||
142 | ret = proj_gpc_base_v(); | ||
143 | break; | ||
144 | case GPU_LIT_GPC_STRIDE: | ||
145 | ret = proj_gpc_stride_v(); | ||
146 | break; | ||
147 | case GPU_LIT_GPC_SHARED_BASE: | ||
148 | ret = proj_gpc_shared_base_v(); | ||
149 | break; | ||
150 | case GPU_LIT_TPC_IN_GPC_BASE: | ||
151 | ret = proj_tpc_in_gpc_base_v(); | ||
152 | break; | ||
153 | case GPU_LIT_TPC_IN_GPC_STRIDE: | ||
154 | ret = proj_tpc_in_gpc_stride_v(); | ||
155 | break; | ||
156 | case GPU_LIT_TPC_IN_GPC_SHARED_BASE: | ||
157 | ret = proj_tpc_in_gpc_shared_base_v(); | ||
158 | break; | ||
159 | case GPU_LIT_PPC_IN_GPC_BASE: | ||
160 | ret = proj_ppc_in_gpc_base_v(); | ||
161 | break; | ||
162 | case GPU_LIT_PPC_IN_GPC_STRIDE: | ||
163 | ret = proj_ppc_in_gpc_stride_v(); | ||
164 | break; | ||
165 | case GPU_LIT_PPC_IN_GPC_SHARED_BASE: | ||
166 | ret = proj_ppc_in_gpc_shared_base_v(); | ||
167 | break; | ||
168 | case GPU_LIT_ROP_BASE: | ||
169 | ret = proj_rop_base_v(); | ||
170 | break; | ||
171 | case GPU_LIT_ROP_STRIDE: | ||
172 | ret = proj_rop_stride_v(); | ||
173 | break; | ||
174 | case GPU_LIT_ROP_SHARED_BASE: | ||
175 | ret = proj_rop_shared_base_v(); | ||
176 | break; | ||
177 | case GPU_LIT_HOST_NUM_ENGINES: | ||
178 | ret = proj_host_num_engines_v(); | ||
179 | break; | ||
180 | case GPU_LIT_HOST_NUM_PBDMA: | ||
181 | ret = proj_host_num_pbdma_v(); | ||
182 | break; | ||
183 | case GPU_LIT_LTC_STRIDE: | ||
184 | ret = proj_ltc_stride_v(); | ||
185 | break; | ||
186 | case GPU_LIT_LTS_STRIDE: | ||
187 | ret = proj_lts_stride_v(); | ||
188 | break; | ||
189 | case GPU_LIT_NUM_FBPAS: | ||
190 | ret = proj_scal_litter_num_fbpas_v(); | ||
191 | break; | ||
192 | case GPU_LIT_FBPA_SHARED_BASE: | ||
193 | ret = proj_fbpa_shared_base_v(); | ||
194 | break; | ||
195 | case GPU_LIT_FBPA_BASE: | ||
196 | ret = proj_fbpa_base_v(); | ||
197 | break; | ||
198 | case GPU_LIT_FBPA_STRIDE: | ||
199 | ret = proj_fbpa_stride_v(); | ||
200 | break; | ||
201 | case GPU_LIT_SM_PRI_STRIDE: | ||
202 | ret = proj_sm_stride_v(); | ||
203 | break; | ||
204 | case GPU_LIT_SMPC_PRI_BASE: | ||
205 | ret = proj_smpc_base_v(); | ||
206 | break; | ||
207 | case GPU_LIT_SMPC_PRI_SHARED_BASE: | ||
208 | ret = proj_smpc_shared_base_v(); | ||
209 | break; | ||
210 | case GPU_LIT_SMPC_PRI_UNIQUE_BASE: | ||
211 | ret = proj_smpc_unique_base_v(); | ||
212 | break; | ||
213 | case GPU_LIT_SMPC_PRI_STRIDE: | ||
214 | ret = proj_smpc_stride_v(); | ||
215 | break; | ||
216 | case GPU_LIT_TWOD_CLASS: | ||
217 | ret = FERMI_TWOD_A; | ||
218 | break; | ||
219 | case GPU_LIT_THREED_CLASS: | ||
220 | ret = VOLTA_A; | ||
221 | break; | ||
222 | case GPU_LIT_COMPUTE_CLASS: | ||
223 | ret = VOLTA_COMPUTE_A; | ||
224 | break; | ||
225 | case GPU_LIT_GPFIFO_CLASS: | ||
226 | ret = VOLTA_CHANNEL_GPFIFO_A; | ||
227 | break; | ||
228 | case GPU_LIT_I2M_CLASS: | ||
229 | ret = KEPLER_INLINE_TO_MEMORY_B; | ||
230 | break; | ||
231 | case GPU_LIT_DMA_COPY_CLASS: | ||
232 | ret = VOLTA_DMA_COPY_A; | ||
233 | break; | ||
234 | default: | ||
235 | break; | ||
236 | } | ||
237 | |||
238 | return ret; | ||
239 | } | ||
240 | |||
241 | int gv100_init_gpu_characteristics(struct gk20a *g) | ||
242 | { | ||
243 | int err; | ||
244 | |||
245 | err = gk20a_init_gpu_characteristics(g); | ||
246 | if (err) | ||
247 | return err; | ||
248 | |||
249 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true); | ||
250 | |||
251 | return 0; | ||
252 | } | ||
253 | |||
254 | |||
255 | |||
256 | static const struct gpu_ops gv100_ops = { | ||
257 | .bios = { | ||
258 | .init = gp106_bios_init, | ||
259 | .preos_wait_for_halt = gv100_bios_preos_wait_for_halt, | ||
260 | .preos_reload_check = gv100_bios_preos_reload_check, | ||
261 | }, | ||
262 | .ltc = { | ||
263 | .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, | ||
264 | .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, | ||
265 | .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, | ||
266 | .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, | ||
267 | .init_cbc = NULL, | ||
268 | .init_fs_state = gv11b_ltc_init_fs_state, | ||
269 | .init_comptags = gp10b_ltc_init_comptags, | ||
270 | .cbc_ctrl = gm20b_ltc_cbc_ctrl, | ||
271 | .isr = gv11b_ltc_isr, | ||
272 | .cbc_fix_config = NULL, | ||
273 | .flush = gm20b_flush_ltc, | ||
274 | .set_enabled = gp10b_ltc_set_enabled, | ||
275 | }, | ||
276 | .ce2 = { | ||
277 | .isr_stall = gv11b_ce_isr, | ||
278 | .isr_nonstall = gp10b_ce_nonstall_isr, | ||
279 | .get_num_pce = gv11b_ce_get_num_pce, | ||
280 | }, | ||
281 | .gr = { | ||
282 | .get_patch_slots = gr_gv100_get_patch_slots, | ||
283 | .init_gpc_mmu = gr_gv11b_init_gpc_mmu, | ||
284 | .bundle_cb_defaults = gr_gv100_bundle_cb_defaults, | ||
285 | .cb_size_default = gr_gv100_cb_size_default, | ||
286 | .calc_global_ctx_buffer_size = | ||
287 | gr_gv11b_calc_global_ctx_buffer_size, | ||
288 | .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb, | ||
289 | .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, | ||
290 | .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, | ||
291 | .commit_global_pagepool = gr_gp10b_commit_global_pagepool, | ||
292 | .handle_sw_method = gr_gv11b_handle_sw_method, | ||
293 | .set_alpha_circular_buffer_size = | ||
294 | gr_gv11b_set_alpha_circular_buffer_size, | ||
295 | .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size, | ||
296 | .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions, | ||
297 | .is_valid_class = gr_gv11b_is_valid_class, | ||
298 | .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class, | ||
299 | .is_valid_compute_class = gr_gv11b_is_valid_compute_class, | ||
300 | .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, | ||
301 | .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, | ||
302 | .init_fs_state = gr_gv11b_init_fs_state, | ||
303 | .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, | ||
304 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, | ||
305 | .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode, | ||
306 | .set_gpc_tpc_mask = gr_gv100_set_gpc_tpc_mask, | ||
307 | .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, | ||
308 | .free_channel_ctx = gk20a_free_channel_ctx, | ||
309 | .alloc_obj_ctx = gk20a_alloc_obj_ctx, | ||
310 | .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull, | ||
311 | .get_zcull_info = gr_gk20a_get_zcull_info, | ||
312 | .is_tpc_addr = gr_gm20b_is_tpc_addr, | ||
313 | .get_tpc_num = gr_gm20b_get_tpc_num, | ||
314 | .detect_sm_arch = gr_gv11b_detect_sm_arch, | ||
315 | .add_zbc_color = gr_gp10b_add_zbc_color, | ||
316 | .add_zbc_depth = gr_gp10b_add_zbc_depth, | ||
317 | .zbc_set_table = gk20a_gr_zbc_set_table, | ||
318 | .zbc_query_table = gr_gk20a_query_zbc, | ||
319 | .pmu_save_zbc = gk20a_pmu_save_zbc, | ||
320 | .add_zbc = gr_gk20a_add_zbc, | ||
321 | .pagepool_default_size = gr_gv11b_pagepool_default_size, | ||
322 | .init_ctx_state = gr_gp10b_init_ctx_state, | ||
323 | .alloc_gr_ctx = gr_gp10b_alloc_gr_ctx, | ||
324 | .free_gr_ctx = gr_gp10b_free_gr_ctx, | ||
325 | .update_ctxsw_preemption_mode = | ||
326 | gr_gp10b_update_ctxsw_preemption_mode, | ||
327 | .dump_gr_regs = gr_gv11b_dump_gr_status_regs, | ||
328 | .update_pc_sampling = gr_gm20b_update_pc_sampling, | ||
329 | .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask, | ||
330 | .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp, | ||
331 | .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc, | ||
332 | .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, | ||
333 | .get_max_fbps_count = gr_gm20b_get_max_fbps_count, | ||
334 | .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, | ||
335 | .wait_empty = gr_gv11b_wait_empty, | ||
336 | .init_cyclestats = gr_gm20b_init_cyclestats, | ||
337 | .set_sm_debug_mode = gv11b_gr_set_sm_debug_mode, | ||
338 | .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, | ||
339 | .bpt_reg_info = gv11b_gr_bpt_reg_info, | ||
340 | .get_access_map = gr_gv11b_get_access_map, | ||
341 | .handle_fecs_error = gr_gv11b_handle_fecs_error, | ||
342 | .handle_sm_exception = gr_gk20a_handle_sm_exception, | ||
343 | .handle_tex_exception = gr_gv11b_handle_tex_exception, | ||
344 | .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions, | ||
345 | .enable_exceptions = gr_gv11b_enable_exceptions, | ||
346 | .get_lrf_tex_ltc_dram_override = get_ecc_override_val, | ||
347 | .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, | ||
348 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, | ||
349 | .record_sm_error_state = gv11b_gr_record_sm_error_state, | ||
350 | .update_sm_error_state = gv11b_gr_update_sm_error_state, | ||
351 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, | ||
352 | .suspend_contexts = gr_gp10b_suspend_contexts, | ||
353 | .resume_contexts = gr_gk20a_resume_contexts, | ||
354 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, | ||
355 | .init_sm_id_table = gr_gv100_init_sm_id_table, | ||
356 | .load_smid_config = gr_gv11b_load_smid_config, | ||
357 | .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, | ||
358 | .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, | ||
359 | .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr, | ||
360 | .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr, | ||
361 | .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr, | ||
362 | .setup_rop_mapping = gr_gv11b_setup_rop_mapping, | ||
363 | .program_zcull_mapping = gr_gv11b_program_zcull_mapping, | ||
364 | .commit_global_timeslice = gr_gv11b_commit_global_timeslice, | ||
365 | .commit_inst = gr_gv11b_commit_inst, | ||
366 | .write_zcull_ptr = gr_gv11b_write_zcull_ptr, | ||
367 | .write_pm_ptr = gr_gv11b_write_pm_ptr, | ||
368 | .init_elcg_mode = gr_gv11b_init_elcg_mode, | ||
369 | .load_tpc_mask = gr_gv11b_load_tpc_mask, | ||
370 | .inval_icache = gr_gk20a_inval_icache, | ||
371 | .trigger_suspend = gv11b_gr_sm_trigger_suspend, | ||
372 | .wait_for_pause = gr_gk20a_wait_for_pause, | ||
373 | .resume_from_pause = gv11b_gr_resume_from_pause, | ||
374 | .clear_sm_errors = gr_gk20a_clear_sm_errors, | ||
375 | .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, | ||
376 | .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel, | ||
377 | .sm_debugger_attached = gv11b_gr_sm_debugger_attached, | ||
378 | .suspend_single_sm = gv11b_gr_suspend_single_sm, | ||
379 | .suspend_all_sms = gv11b_gr_suspend_all_sms, | ||
380 | .resume_single_sm = gv11b_gr_resume_single_sm, | ||
381 | .resume_all_sms = gv11b_gr_resume_all_sms, | ||
382 | .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr, | ||
383 | .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr, | ||
384 | .get_sm_no_lock_down_hww_global_esr_mask = | ||
385 | gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask, | ||
386 | .lock_down_sm = gv11b_gr_lock_down_sm, | ||
387 | .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down, | ||
388 | .clear_sm_hww = gv11b_gr_clear_sm_hww, | ||
389 | .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, | ||
390 | .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, | ||
391 | .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, | ||
392 | .set_boosted_ctx = gr_gp10b_set_boosted_ctx, | ||
393 | .set_preemption_mode = gr_gp10b_set_preemption_mode, | ||
394 | .set_czf_bypass = NULL, | ||
395 | .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception, | ||
396 | .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va, | ||
397 | .init_preemption_state = NULL, | ||
398 | .update_boosted_ctx = gr_gp10b_update_boosted_ctx, | ||
399 | .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, | ||
400 | .create_gr_sysfs = gr_gv11b_create_sysfs, | ||
401 | .set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode, | ||
402 | .is_etpc_addr = gv11b_gr_pri_is_etpc_addr, | ||
403 | .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table, | ||
404 | .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, | ||
405 | .zbc_s_query_table = gr_gv11b_zbc_s_query_table, | ||
406 | .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl, | ||
407 | .handle_gpc_gpcmmu_exception = | ||
408 | gr_gv11b_handle_gpc_gpcmmu_exception, | ||
409 | .add_zbc_type_s = gr_gv11b_add_zbc_type_s, | ||
410 | .get_egpc_base = gv11b_gr_get_egpc_base, | ||
411 | .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num, | ||
412 | .handle_gpc_gpccs_exception = | ||
413 | gr_gv11b_handle_gpc_gpccs_exception, | ||
414 | .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl, | ||
415 | .access_smpc_reg = gv11b_gr_access_smpc_reg, | ||
416 | .is_egpc_addr = gv11b_gr_pri_is_egpc_addr, | ||
417 | .add_zbc_s = gr_gv11b_add_zbc_stencil, | ||
418 | .handle_gcc_exception = gr_gv11b_handle_gcc_exception, | ||
419 | .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle, | ||
420 | .handle_tpc_sm_ecc_exception = | ||
421 | gr_gv11b_handle_tpc_sm_ecc_exception, | ||
422 | .decode_egpc_addr = gv11b_gr_decode_egpc_addr, | ||
423 | }, | ||
424 | .fb = { | ||
425 | .reset = gv100_fb_reset, | ||
426 | .init_hw = gk20a_fb_init_hw, | ||
427 | .init_fs_state = NULL, | ||
428 | .set_mmu_page_size = gm20b_fb_set_mmu_page_size, | ||
429 | .set_use_full_comp_tag_line = | ||
430 | gm20b_fb_set_use_full_comp_tag_line, | ||
431 | .compression_page_size = gp10b_fb_compression_page_size, | ||
432 | .compressible_page_size = gp10b_fb_compressible_page_size, | ||
433 | .vpr_info_fetch = gm20b_fb_vpr_info_fetch, | ||
434 | .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, | ||
435 | .read_wpr_info = gm20b_fb_read_wpr_info, | ||
436 | .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, | ||
437 | .set_debug_mode = gm20b_fb_set_debug_mode, | ||
438 | .tlb_invalidate = gk20a_fb_tlb_invalidate, | ||
439 | .hub_isr = gv11b_fb_hub_isr, | ||
440 | .mem_unlock = gv100_fb_memory_unlock, | ||
441 | }, | ||
442 | .fifo = { | ||
443 | .get_preempt_timeout = gv100_fifo_get_preempt_timeout, | ||
444 | .init_fifo_setup_hw = gv11b_init_fifo_setup_hw, | ||
445 | .bind_channel = channel_gm20b_bind, | ||
446 | .unbind_channel = channel_gv11b_unbind, | ||
447 | .disable_channel = gk20a_fifo_disable_channel, | ||
448 | .enable_channel = gk20a_fifo_enable_channel, | ||
449 | .alloc_inst = gk20a_fifo_alloc_inst, | ||
450 | .free_inst = gk20a_fifo_free_inst, | ||
451 | .setup_ramfc = channel_gv11b_setup_ramfc, | ||
452 | .channel_set_timeslice = gk20a_fifo_set_timeslice, | ||
453 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, | ||
454 | .setup_userd = gk20a_fifo_setup_userd, | ||
455 | .userd_gp_get = gv11b_userd_gp_get, | ||
456 | .userd_gp_put = gv11b_userd_gp_put, | ||
457 | .userd_pb_get = gv11b_userd_pb_get, | ||
458 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, | ||
459 | .preempt_channel = gv11b_fifo_preempt_channel, | ||
460 | .preempt_tsg = gv11b_fifo_preempt_tsg, | ||
461 | .enable_tsg = gv11b_fifo_enable_tsg, | ||
462 | .disable_tsg = gk20a_disable_tsg, | ||
463 | .tsg_verify_channel_status = gk20a_fifo_tsg_unbind_channel_verify_status, | ||
464 | .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, | ||
465 | .tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted, | ||
466 | .update_runlist = gk20a_fifo_update_runlist, | ||
467 | .trigger_mmu_fault = NULL, | ||
468 | .get_mmu_fault_info = NULL, | ||
469 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, | ||
470 | .get_num_fifos = gv100_fifo_get_num_fifos, | ||
471 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, | ||
472 | .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, | ||
473 | .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, | ||
474 | .force_reset_ch = gk20a_fifo_force_reset_ch, | ||
475 | .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, | ||
476 | .device_info_data_parse = gp10b_device_info_data_parse, | ||
477 | .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, | ||
478 | .init_engine_info = gk20a_fifo_init_engine_info, | ||
479 | .runlist_entry_size = ram_rl_entry_size_v, | ||
480 | .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry, | ||
481 | .get_ch_runlist_entry = gv11b_get_ch_runlist_entry, | ||
482 | .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, | ||
483 | .dump_pbdma_status = gk20a_dump_pbdma_status, | ||
484 | .dump_eng_status = gv11b_dump_eng_status, | ||
485 | .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc, | ||
486 | .intr_0_error_mask = gv11b_fifo_intr_0_error_mask, | ||
487 | .is_preempt_pending = gv11b_fifo_is_preempt_pending, | ||
488 | .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, | ||
489 | .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, | ||
490 | .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, | ||
491 | .handle_sched_error = gv11b_fifo_handle_sched_error, | ||
492 | .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, | ||
493 | .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1, | ||
494 | .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers, | ||
495 | .deinit_eng_method_buffers = | ||
496 | gv11b_fifo_deinit_eng_method_buffers, | ||
497 | .tsg_bind_channel = gk20a_tsg_bind_channel, | ||
498 | .tsg_unbind_channel = gk20a_tsg_unbind_channel, | ||
499 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
500 | .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, | ||
501 | .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, | ||
502 | .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd, | ||
503 | .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, | ||
504 | .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, | ||
505 | .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, | ||
506 | #endif | ||
507 | .resetup_ramfc = NULL, | ||
508 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, | ||
509 | .free_channel_ctx_header = gv11b_free_subctx_header, | ||
510 | .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg, | ||
511 | .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, | ||
512 | }, | ||
513 | .gr_ctx = { | ||
514 | .get_netlist_name = gr_gv100_get_netlist_name, | ||
515 | .is_fw_defined = gr_gv100_is_firmware_defined, | ||
516 | }, | ||
517 | #ifdef CONFIG_GK20A_CTXSW_TRACE | ||
518 | .fecs_trace = { | ||
519 | .alloc_user_buffer = NULL, | ||
520 | .free_user_buffer = NULL, | ||
521 | .mmap_user_buffer = NULL, | ||
522 | .init = NULL, | ||
523 | .deinit = NULL, | ||
524 | .enable = NULL, | ||
525 | .disable = NULL, | ||
526 | .is_enabled = NULL, | ||
527 | .reset = NULL, | ||
528 | .flush = NULL, | ||
529 | .poll = NULL, | ||
530 | .bind_channel = NULL, | ||
531 | .unbind_channel = NULL, | ||
532 | .max_entries = NULL, | ||
533 | }, | ||
534 | #endif /* CONFIG_GK20A_CTXSW_TRACE */ | ||
535 | .mm = { | ||
536 | .support_sparse = gm20b_mm_support_sparse, | ||
537 | .gmmu_map = gk20a_locked_gmmu_map, | ||
538 | .gmmu_unmap = gk20a_locked_gmmu_unmap, | ||
539 | .vm_bind_channel = gk20a_vm_bind_channel, | ||
540 | .fb_flush = gk20a_mm_fb_flush, | ||
541 | .l2_invalidate = gk20a_mm_l2_invalidate, | ||
542 | .l2_flush = gk20a_mm_l2_flush, | ||
543 | .cbc_clean = gk20a_mm_cbc_clean, | ||
544 | .set_big_page_size = gm20b_mm_set_big_page_size, | ||
545 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, | ||
546 | .get_default_big_page_size = gp10b_mm_get_default_big_page_size, | ||
547 | .gpu_phys_addr = gv11b_gpu_phys_addr, | ||
548 | .get_mmu_levels = gp10b_mm_get_mmu_levels, | ||
549 | .get_vidmem_size = gv100_mm_get_vidmem_size, | ||
550 | .init_pdb = gp10b_mm_init_pdb, | ||
551 | .init_mm_setup_hw = gv11b_init_mm_setup_hw, | ||
552 | .is_bar1_supported = gv11b_mm_is_bar1_supported, | ||
553 | .alloc_inst_block = gk20a_alloc_inst_block, | ||
554 | .init_inst_block = gv11b_init_inst_block, | ||
555 | .mmu_fault_pending = gv11b_mm_mmu_fault_pending, | ||
556 | .get_kind_invalid = gm20b_get_kind_invalid, | ||
557 | .get_kind_pitch = gm20b_get_kind_pitch, | ||
558 | .init_bar2_vm = gb10b_init_bar2_vm, | ||
559 | .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, | ||
560 | .remove_bar2_vm = gv11b_mm_remove_bar2_vm, | ||
561 | .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, | ||
562 | .get_flush_retries = gv100_mm_get_flush_retries, | ||
563 | }, | ||
564 | .pramin = { | ||
565 | .enter = gk20a_pramin_enter, | ||
566 | .exit = gk20a_pramin_exit, | ||
567 | .data032_r = pram_data032_r, | ||
568 | }, | ||
569 | .pmu = { | ||
570 | .init_wpr_region = gm20b_pmu_init_acr, | ||
571 | .load_lsfalcon_ucode = gp106_load_falcon_ucode, | ||
572 | .is_lazy_bootstrap = gp106_is_lazy_bootstrap, | ||
573 | .is_priv_load = gp106_is_priv_load, | ||
574 | .prepare_ucode = gp106_prepare_ucode_blob, | ||
575 | .pmu_setup_hw_and_bootstrap = gp106_bootstrap_hs_flcn, | ||
576 | .get_wpr = gp106_wpr_info, | ||
577 | .alloc_blob_space = gp106_alloc_blob_space, | ||
578 | .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg, | ||
579 | .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc, | ||
580 | .falcon_wait_for_halt = sec2_wait_for_halt, | ||
581 | .falcon_clear_halt_interrupt_status = | ||
582 | sec2_clear_halt_interrupt_status, | ||
583 | .init_falcon_setup_hw = init_sec2_setup_hw1, | ||
584 | .pmu_queue_tail = gk20a_pmu_queue_tail, | ||
585 | .pmu_get_queue_head = pwr_pmu_queue_head_r, | ||
586 | .pmu_mutex_release = gk20a_pmu_mutex_release, | ||
587 | .is_pmu_supported = gp106_is_pmu_supported, | ||
588 | .pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list, | ||
589 | .pmu_elpg_statistics = gp106_pmu_elpg_statistics, | ||
590 | .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, | ||
591 | .pmu_is_lpwr_feature_supported = | ||
592 | gp106_pmu_is_lpwr_feature_supported, | ||
593 | .pmu_msgq_tail = gk20a_pmu_msgq_tail, | ||
594 | .pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list, | ||
595 | .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, | ||
596 | .pmu_queue_head = gk20a_pmu_queue_head, | ||
597 | .pmu_pg_param_post_init = nvgpu_lpwr_post_init, | ||
598 | .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, | ||
599 | .pmu_pg_init_param = gp106_pg_param_init, | ||
600 | .reset_engine = gp106_pmu_engine_reset, | ||
601 | .write_dmatrfbase = gp10b_write_dmatrfbase, | ||
602 | .pmu_mutex_size = pwr_pmu_mutex__size_1_v, | ||
603 | .is_engine_in_reset = gp106_pmu_is_engine_in_reset, | ||
604 | .pmu_get_queue_tail = pwr_pmu_queue_tail_r, | ||
605 | }, | ||
606 | .clk = { | ||
607 | .init_clk_support = gp106_init_clk_support, | ||
608 | .get_crystal_clk_hz = gp106_crystal_clk_hz, | ||
609 | .measure_freq = gp106_clk_measure_freq, | ||
610 | .suspend_clk_support = gp106_suspend_clk_support, | ||
611 | }, | ||
612 | .clk_arb = { | ||
613 | .get_arbiter_clk_domains = gp106_get_arbiter_clk_domains, | ||
614 | .get_arbiter_clk_range = gp106_get_arbiter_clk_range, | ||
615 | .get_arbiter_clk_default = gp106_get_arbiter_clk_default, | ||
616 | .get_current_pstate = nvgpu_clk_arb_get_current_pstate, | ||
617 | }, | ||
618 | .regops = { | ||
619 | .get_global_whitelist_ranges = | ||
620 | gv100_get_global_whitelist_ranges, | ||
621 | .get_global_whitelist_ranges_count = | ||
622 | gv100_get_global_whitelist_ranges_count, | ||
623 | .get_context_whitelist_ranges = | ||
624 | gv100_get_context_whitelist_ranges, | ||
625 | .get_context_whitelist_ranges_count = | ||
626 | gv100_get_context_whitelist_ranges_count, | ||
627 | .get_runcontrol_whitelist = gv100_get_runcontrol_whitelist, | ||
628 | .get_runcontrol_whitelist_count = | ||
629 | gv100_get_runcontrol_whitelist_count, | ||
630 | .get_runcontrol_whitelist_ranges = | ||
631 | gv100_get_runcontrol_whitelist_ranges, | ||
632 | .get_runcontrol_whitelist_ranges_count = | ||
633 | gv100_get_runcontrol_whitelist_ranges_count, | ||
634 | .get_qctl_whitelist = gv100_get_qctl_whitelist, | ||
635 | .get_qctl_whitelist_count = gv100_get_qctl_whitelist_count, | ||
636 | .get_qctl_whitelist_ranges = gv100_get_qctl_whitelist_ranges, | ||
637 | .get_qctl_whitelist_ranges_count = | ||
638 | gv100_get_qctl_whitelist_ranges_count, | ||
639 | .apply_smpc_war = gv100_apply_smpc_war, | ||
640 | }, | ||
641 | .mc = { | ||
642 | .intr_enable = mc_gv11b_intr_enable, | ||
643 | .intr_unit_config = mc_gp10b_intr_unit_config, | ||
644 | .isr_stall = mc_gp10b_isr_stall, | ||
645 | .intr_stall = mc_gp10b_intr_stall, | ||
646 | .intr_stall_pause = mc_gp10b_intr_stall_pause, | ||
647 | .intr_stall_resume = mc_gp10b_intr_stall_resume, | ||
648 | .intr_nonstall = mc_gp10b_intr_nonstall, | ||
649 | .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, | ||
650 | .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, | ||
651 | .enable = gk20a_mc_enable, | ||
652 | .disable = gk20a_mc_disable, | ||
653 | .reset = gk20a_mc_reset, | ||
654 | .boot_0 = gk20a_mc_boot_0, | ||
655 | .is_intr1_pending = mc_gp10b_is_intr1_pending, | ||
656 | .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, | ||
657 | }, | ||
658 | .debug = { | ||
659 | .show_dump = gk20a_debug_show_dump, | ||
660 | }, | ||
661 | .dbg_session_ops = { | ||
662 | .exec_reg_ops = exec_regops_gk20a, | ||
663 | .dbg_set_powergate = dbg_set_powergate, | ||
664 | .check_and_set_global_reservation = | ||
665 | nvgpu_check_and_set_global_reservation, | ||
666 | .check_and_set_context_reservation = | ||
667 | nvgpu_check_and_set_context_reservation, | ||
668 | .release_profiler_reservation = | ||
669 | nvgpu_release_profiler_reservation, | ||
670 | .perfbuffer_enable = gv11b_perfbuf_enable_locked, | ||
671 | .perfbuffer_disable = gv11b_perfbuf_disable_locked, | ||
672 | }, | ||
673 | .bus = { | ||
674 | .init_hw = gk20a_bus_init_hw, | ||
675 | .isr = gk20a_bus_isr, | ||
676 | .read_ptimer = gk20a_read_ptimer, | ||
677 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, | ||
678 | .bar1_bind = NULL, | ||
679 | }, | ||
680 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
681 | .css = { | ||
682 | .enable_snapshot = gv11b_css_hw_enable_snapshot, | ||
683 | .disable_snapshot = gv11b_css_hw_disable_snapshot, | ||
684 | .check_data_available = gv11b_css_hw_check_data_available, | ||
685 | .set_handled_snapshots = css_hw_set_handled_snapshots, | ||
686 | .allocate_perfmon_ids = css_gr_allocate_perfmon_ids, | ||
687 | .release_perfmon_ids = css_gr_release_perfmon_ids, | ||
688 | }, | ||
689 | #endif | ||
690 | .xve = { | ||
691 | .get_speed = xve_get_speed_gp106, | ||
692 | .set_speed = xve_set_speed_gp106, | ||
693 | .available_speeds = xve_available_speeds_gp106, | ||
694 | .xve_readl = xve_xve_readl_gp106, | ||
695 | .xve_writel = xve_xve_writel_gp106, | ||
696 | .disable_aspm = xve_disable_aspm_gp106, | ||
697 | .reset_gpu = xve_reset_gpu_gp106, | ||
698 | #if defined(CONFIG_PCI_MSI) | ||
699 | .rearm_msi = xve_rearm_msi_gp106, | ||
700 | #endif | ||
701 | .enable_shadow_rom = xve_enable_shadow_rom_gp106, | ||
702 | .disable_shadow_rom = xve_disable_shadow_rom_gp106, | ||
703 | }, | ||
704 | .falcon = { | ||
705 | .falcon_hal_sw_init = gp106_falcon_hal_sw_init, | ||
706 | }, | ||
707 | .priv_ring = { | ||
708 | .isr = gp10b_priv_ring_isr, | ||
709 | }, | ||
710 | .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, | ||
711 | .get_litter_value = gv100_get_litter_value, | ||
712 | }; | ||
713 | |||
714 | int gv100_init_hal(struct gk20a *g) | ||
715 | { | ||
716 | struct gpu_ops *gops = &g->ops; | ||
717 | |||
718 | gops->bios = gv100_ops.bios; | ||
719 | gops->ltc = gv100_ops.ltc; | ||
720 | gops->ce2 = gv100_ops.ce2; | ||
721 | gops->gr = gv100_ops.gr; | ||
722 | gops->fb = gv100_ops.fb; | ||
723 | gops->clock_gating = gv100_ops.clock_gating; | ||
724 | gops->fifo = gv100_ops.fifo; | ||
725 | gops->gr_ctx = gv100_ops.gr_ctx; | ||
726 | gops->mm = gv100_ops.mm; | ||
727 | #ifdef CONFIG_GK20A_CTXSW_TRACE | ||
728 | gops->fecs_trace = gv100_ops.fecs_trace; | ||
729 | #endif | ||
730 | gops->pramin = gv100_ops.pramin; | ||
731 | gops->therm = gv100_ops.therm; | ||
732 | gops->pmu = gv100_ops.pmu; | ||
733 | gops->regops = gv100_ops.regops; | ||
734 | gops->mc = gv100_ops.mc; | ||
735 | gops->debug = gv100_ops.debug; | ||
736 | gops->dbg_session_ops = gv100_ops.dbg_session_ops; | ||
737 | gops->bus = gv100_ops.bus; | ||
738 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
739 | gops->css = gv100_ops.css; | ||
740 | #endif | ||
741 | gops->xve = gv100_ops.xve; | ||
742 | gops->falcon = gv100_ops.falcon; | ||
743 | gops->priv_ring = gv100_ops.priv_ring; | ||
744 | |||
745 | /* clocks */ | ||
746 | gops->clk.init_clk_support = gv100_ops.clk.init_clk_support; | ||
747 | gops->clk.get_crystal_clk_hz = gv100_ops.clk.get_crystal_clk_hz; | ||
748 | gops->clk.measure_freq = gv100_ops.clk.measure_freq; | ||
749 | gops->clk.suspend_clk_support = gv100_ops.clk.suspend_clk_support; | ||
750 | |||
751 | /* Lone functions */ | ||
752 | gops->chip_init_gpu_characteristics = | ||
753 | gv100_ops.chip_init_gpu_characteristics; | ||
754 | gops->get_litter_value = gv100_ops.get_litter_value; | ||
755 | |||
756 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | ||
757 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
758 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
759 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); | ||
760 | /* for now */ | ||
761 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | ||
762 | |||
763 | g->pmu_lsf_pmu_wpr_init_done = 0; | ||
764 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; | ||
765 | |||
766 | g->name = "gv10x"; | ||
767 | |||
768 | return 0; | ||
769 | } | ||