summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gv100/gr_gv100.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/nvgpu/gv100/gr_gv100.c')
-rw-r--r--drivers/gpu/nvgpu/gv100/gr_gv100.c38
1 files changed, 0 insertions, 38 deletions
diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c
index 79526947..d5ace998 100644
--- a/drivers/gpu/nvgpu/gv100/gr_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c
@@ -35,7 +35,6 @@
35#include "gv11b/subctx_gv11b.h" 35#include "gv11b/subctx_gv11b.h"
36 36
37#include <nvgpu/hw/gv100/hw_gr_gv100.h> 37#include <nvgpu/hw/gv100/hw_gr_gv100.h>
38#include <nvgpu/hw/gv100/hw_fb_gv100.h>
39#include <nvgpu/hw/gv100/hw_proj_gv100.h> 38#include <nvgpu/hw/gv100/hw_proj_gv100.h>
40#include <nvgpu/hw/gv100/hw_top_gv100.h> 39#include <nvgpu/hw/gv100/hw_top_gv100.h>
41#include <nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h> 40#include <nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h>
@@ -286,43 +285,6 @@ exit_build_table:
286 return err; 285 return err;
287} 286}
288 287
289void gr_gv100_init_gpc_mmu(struct gk20a *g)
290{
291 u32 temp;
292
293 nvgpu_log_info(g, "initialize gpc mmu");
294
295 if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
296 /* Bypass MMU check for non-secure boot. For
297 * secure-boot,this register write has no-effect */
298 gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff);
299 }
300 temp = gk20a_readl(g, fb_mmu_ctrl_r());
301 temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() |
302 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() |
303 gr_gpcs_pri_mmu_ctrl_vol_fault_m() |
304 gr_gpcs_pri_mmu_ctrl_comp_fault_m() |
305 gr_gpcs_pri_mmu_ctrl_miss_gran_m() |
306 gr_gpcs_pri_mmu_ctrl_cache_mode_m() |
307 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() |
308 gr_gpcs_pri_mmu_ctrl_mmu_vol_m() |
309 gr_gpcs_pri_mmu_ctrl_mmu_disable_m()|
310 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m();
311
312 gk20a_writel(g, gr_gpcs_pri_mmu_ctrl_r(), temp);
313 nvgpu_log_info(g, "mmu_ctrl_r = 0x%08x", temp);
314
315 gk20a_writel(g, gr_gpcs_pri_mmu_pm_unit_mask_r(), 0);
316 gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0);
317
318 gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(),
319 gk20a_readl(g, fb_mmu_debug_ctrl_r()));
320 gk20a_writel(g, gr_gpcs_pri_mmu_debug_wr_r(),
321 gk20a_readl(g, fb_mmu_debug_wr_r()));
322 gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(),
323 gk20a_readl(g, fb_mmu_debug_rd_r()));
324}
325
326u32 gr_gv100_get_patch_slots(struct gk20a *g) 288u32 gr_gv100_get_patch_slots(struct gk20a *g)
327{ 289{
328 struct gr_gk20a *gr = &g->gr; 290 struct gr_gk20a *gr = &g->gr;