diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gv100/gr_gv100.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/gr_gv100.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c index 98e61eb0..2180fa1c 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c | |||
@@ -34,6 +34,7 @@ | |||
34 | #include "gv11b/subctx_gv11b.h" | 34 | #include "gv11b/subctx_gv11b.h" |
35 | 35 | ||
36 | #include <nvgpu/hw/gv100/hw_gr_gv100.h> | 36 | #include <nvgpu/hw/gv100/hw_gr_gv100.h> |
37 | #include <nvgpu/hw/gv100/hw_fb_gv100.h> | ||
37 | #include <nvgpu/hw/gv100/hw_proj_gv100.h> | 38 | #include <nvgpu/hw/gv100/hw_proj_gv100.h> |
38 | #include <nvgpu/hw/gv100/hw_fuse_gv100.h> | 39 | #include <nvgpu/hw/gv100/hw_fuse_gv100.h> |
39 | 40 | ||
@@ -280,6 +281,43 @@ exit_build_table: | |||
280 | return err; | 281 | return err; |
281 | } | 282 | } |
282 | 283 | ||
284 | void gr_gv100_init_gpc_mmu(struct gk20a *g) | ||
285 | { | ||
286 | u32 temp; | ||
287 | |||
288 | nvgpu_log_info(g, "initialize gpc mmu"); | ||
289 | |||
290 | if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | ||
291 | /* Bypass MMU check for non-secure boot. For | ||
292 | * secure-boot,this register write has no-effect */ | ||
293 | gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff); | ||
294 | } | ||
295 | temp = gk20a_readl(g, fb_mmu_ctrl_r()); | ||
296 | temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() | | ||
297 | gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() | | ||
298 | gr_gpcs_pri_mmu_ctrl_vol_fault_m() | | ||
299 | gr_gpcs_pri_mmu_ctrl_comp_fault_m() | | ||
300 | gr_gpcs_pri_mmu_ctrl_miss_gran_m() | | ||
301 | gr_gpcs_pri_mmu_ctrl_cache_mode_m() | | ||
302 | gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() | | ||
303 | gr_gpcs_pri_mmu_ctrl_mmu_vol_m() | | ||
304 | gr_gpcs_pri_mmu_ctrl_mmu_disable_m()| | ||
305 | gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m(); | ||
306 | |||
307 | gk20a_writel(g, gr_gpcs_pri_mmu_ctrl_r(), temp); | ||
308 | nvgpu_log_info(g, "mmu_ctrl_r = 0x%08x", temp); | ||
309 | |||
310 | gk20a_writel(g, gr_gpcs_pri_mmu_pm_unit_mask_r(), 0); | ||
311 | gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0); | ||
312 | |||
313 | gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), | ||
314 | gk20a_readl(g, fb_mmu_debug_ctrl_r())); | ||
315 | gk20a_writel(g, gr_gpcs_pri_mmu_debug_wr_r(), | ||
316 | gk20a_readl(g, fb_mmu_debug_wr_r())); | ||
317 | gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(), | ||
318 | gk20a_readl(g, fb_mmu_debug_rd_r())); | ||
319 | } | ||
320 | |||
283 | u32 gr_gv100_get_patch_slots(struct gk20a *g) | 321 | u32 gr_gv100_get_patch_slots(struct gk20a *g) |
284 | { | 322 | { |
285 | struct gr_gk20a *gr = &g->gr; | 323 | struct gr_gk20a *gr = &g->gr; |