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path: root/drivers/gpu/nvgpu/gv100/flcn_gv100.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gv100/flcn_gv100.c')
-rw-r--r--drivers/gpu/nvgpu/gv100/flcn_gv100.c47
1 files changed, 42 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gv100/flcn_gv100.c b/drivers/gpu/nvgpu/gv100/flcn_gv100.c
index 5167e3f0..900d9204 100644
--- a/drivers/gpu/nvgpu/gv100/flcn_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/flcn_gv100.c
@@ -26,29 +26,66 @@
26#include "gk20a/flcn_gk20a.h" 26#include "gk20a/flcn_gk20a.h"
27#include "gp106/flcn_gp106.h" 27#include "gp106/flcn_gp106.h"
28#include "gv100/flcn_gv100.h" 28#include "gv100/flcn_gv100.h"
29#include "gv100/gsp_gv100.h"
29 30
30#include <nvgpu/hw/gv100/hw_falcon_gv100.h> 31#include <nvgpu/hw/gv100/hw_falcon_gv100.h>
32#include <nvgpu/hw/gv100/hw_pgsp_gv100.h>
33
34static void gv100_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn)
35{
36 struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops =
37 &flcn->flcn_engine_dep_ops;
38
39 switch (flcn->flcn_id) {
40 case FALCON_ID_GSPLITE:
41 flcn_eng_dep_ops->reset_eng = gv100_gsp_reset;
42 break;
43 default:
44 flcn_eng_dep_ops->reset_eng = NULL;
45 break;
46 }
47}
48
49static void gv100_falcon_ops(struct nvgpu_falcon *flcn)
50{
51 gk20a_falcon_ops(flcn);
52 gv100_falcon_engine_dependency_ops(flcn);
53}
31 54
32int gv100_falcon_hal_sw_init(struct nvgpu_falcon *flcn) 55int gv100_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
33{ 56{
34 struct gk20a *g = flcn->g; 57 struct gk20a *g = flcn->g;
35 int err = 0; 58 int err = 0;
36 59
37 if (flcn->flcn_id == FALCON_ID_MINION) { 60 switch (flcn->flcn_id) {
61 case FALCON_ID_MINION:
38 flcn->flcn_base = g->nvlink.minion_base; 62 flcn->flcn_base = g->nvlink.minion_base;
39 flcn->is_falcon_supported = true; 63 flcn->is_falcon_supported = true;
40 flcn->is_interrupt_enabled = true; 64 flcn->is_interrupt_enabled = true;
65 break;
66 case FALCON_ID_GSPLITE:
67 flcn->flcn_base = pgsp_falcon_irqsset_r();
68 flcn->is_falcon_supported = true;
69 flcn->is_interrupt_enabled = false;
70 break;
71 default:
72 flcn->is_falcon_supported = false;
73 break;
74 }
41 75
76 if (flcn->is_falcon_supported) {
42 err = nvgpu_mutex_init(&flcn->copy_lock); 77 err = nvgpu_mutex_init(&flcn->copy_lock);
43 if (err != 0) { 78 if (err != 0) {
44 nvgpu_err(g, "Error in flcn.copy_lock mutex initialization"); 79 nvgpu_err(g, "Error in flcn.copy_lock mutex initialization");
45 return err; 80 } else {
81 gv100_falcon_ops(flcn);
46 } 82 }
47
48 gk20a_falcon_ops(flcn);
49 } else { 83 } else {
50 /* 84 /*
51 * Fall back 85 * Forward call to previous chips HAL
86 * to fetch info for requested
87 * falcon as no changes between
88 * current & previous chips.
52 */ 89 */
53 err = gp106_falcon_hal_sw_init(flcn); 90 err = gp106_falcon_hal_sw_init(flcn);
54 } 91 }