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Diffstat (limited to 'drivers/gpu/nvgpu/gv100/fifo_gv100.c')
-rw-r--r--drivers/gpu/nvgpu/gv100/fifo_gv100.c20
1 files changed, 19 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.c b/drivers/gpu/nvgpu/gv100/fifo_gv100.c
index 0b5515f2..e23bc77b 100644
--- a/drivers/gpu/nvgpu/gv100/fifo_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GV100 fifo 2 * GV100 fifo
3 * 3 *
4 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -55,3 +55,21 @@ void gv100_apply_ctxsw_timeout_intr(struct gk20a *g)
55 gk20a_writel(g, fifo_eng_timeout_r(), timeout); 55 gk20a_writel(g, fifo_eng_timeout_r(), timeout);
56} 56}
57 57
58void gv100_fifo_teardown_mask_intr(struct gk20a *g)
59{
60 u32 val;
61
62 val = gk20a_readl(g, fifo_intr_en_0_r());
63 val &= ~(fifo_intr_en_0_sched_error_m());
64 gk20a_writel(g, fifo_intr_en_0_r(), val);
65 gk20a_writel(g, fifo_intr_0_r(), fifo_intr_0_sched_error_reset_f());
66}
67
68void gv100_fifo_teardown_unmask_intr(struct gk20a *g)
69{
70 u32 val;
71
72 val = gk20a_readl(g, fifo_intr_en_0_r());
73 val |= fifo_intr_en_0_sched_error_f(1);
74 gk20a_writel(g, fifo_intr_en_0_r(), val);
75}