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Diffstat (limited to 'drivers/gpu/nvgpu/gv100/fb_gv100.c')
-rw-r--r--drivers/gpu/nvgpu/gv100/fb_gv100.c256
1 files changed, 0 insertions, 256 deletions
diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c
deleted file mode 100644
index 1889268f..00000000
--- a/drivers/gpu/nvgpu/gv100/fb_gv100.c
+++ /dev/null
@@ -1,256 +0,0 @@
1/*
2 * GV100 FB
3 *
4 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include <nvgpu/types.h>
26
27#include <nvgpu/dma.h>
28#include <nvgpu/log.h>
29#include <nvgpu/enabled.h>
30#include <nvgpu/gmmu.h>
31#include <nvgpu/nvgpu_common.h>
32#include <nvgpu/kmem.h>
33#include <nvgpu/nvgpu_mem.h>
34#include <nvgpu/acr/nvgpu_acr.h>
35#include <nvgpu/firmware.h>
36#include <nvgpu/pmu.h>
37#include <nvgpu/falcon.h>
38
39#include "gk20a/gk20a.h"
40#include "gv100/fb_gv100.h"
41#include "gm20b/acr_gm20b.h"
42
43#include <nvgpu/hw/gv100/hw_fb_gv100.h>
44#include <nvgpu/hw/gv100/hw_falcon_gv100.h>
45#include <nvgpu/hw/gv100/hw_mc_gv100.h>
46
47#define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */
48#define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */
49#define MEM_UNLOCK_TIMEOUT 3500 /* msec */
50
51void gv100_fb_reset(struct gk20a *g)
52{
53 u32 val;
54 int retries = HW_SCRUB_TIMEOUT_MAX / HW_SCRUB_TIMEOUT_DEFAULT;
55
56 nvgpu_info(g, "reset gv100 fb");
57
58 /* wait for memory to be accessible */
59 do {
60 u32 w = gk20a_readl(g, fb_niso_scrub_status_r());
61 if (fb_niso_scrub_status_flag_v(w)) {
62 nvgpu_info(g, "done");
63 break;
64 }
65 nvgpu_udelay(HW_SCRUB_TIMEOUT_DEFAULT);
66 } while (--retries);
67
68 val = gk20a_readl(g, fb_mmu_priv_level_mask_r());
69 val &= ~fb_mmu_priv_level_mask_write_violation_m();
70 gk20a_writel(g, fb_mmu_priv_level_mask_r(), val);
71}
72
73void gv100_fb_enable_hub_intr(struct gk20a *g)
74{
75 u32 mask = 0;
76
77 mask = fb_niso_intr_en_set_mmu_other_fault_notify_m() |
78 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m() |
79 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m() |
80 fb_niso_intr_en_set_mmu_replayable_fault_notify_m() |
81 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m();
82
83 gk20a_writel(g, fb_niso_intr_en_set_r(0),
84 mask);
85}
86
87void gv100_fb_disable_hub_intr(struct gk20a *g)
88{
89 u32 mask = 0;
90
91 mask = fb_niso_intr_en_set_mmu_other_fault_notify_m() |
92 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m() |
93 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m() |
94 fb_niso_intr_en_set_mmu_replayable_fault_notify_m() |
95 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m();
96
97 gk20a_writel(g, fb_niso_intr_en_clr_r(0),
98 mask);
99}
100
101int gv100_fb_memory_unlock(struct gk20a *g)
102{
103 struct nvgpu_firmware *mem_unlock_fw = NULL;
104 struct bin_hdr *hsbin_hdr = NULL;
105 struct acr_fw_header *fw_hdr = NULL;
106 u32 *mem_unlock_ucode = NULL;
107 u32 *mem_unlock_ucode_header = NULL;
108 u32 sec_imem_dest = 0;
109 u32 val = 0;
110 int err = 0;
111
112 nvgpu_log_fn(g, " ");
113
114 nvgpu_log_info(g, "fb_mmu_vpr_info = 0x%08x",
115 gk20a_readl(g, fb_mmu_vpr_info_r()));
116 /*
117 * mem_unlock.bin should be written to install
118 * traps even if VPR isn’t actually supported
119 */
120 mem_unlock_fw = nvgpu_request_firmware(g, "mem_unlock.bin", 0);
121 if (!mem_unlock_fw) {
122 nvgpu_err(g, "mem unlock ucode get fail");
123 err = -ENOENT;
124 goto exit;
125 }
126
127 /* Enable nvdec */
128 g->ops.mc.enable(g, mc_enable_nvdec_enabled_f());
129
130 /* nvdec falcon reset */
131 nvgpu_flcn_reset(&g->nvdec_flcn);
132
133 hsbin_hdr = (struct bin_hdr *)mem_unlock_fw->data;
134 fw_hdr = (struct acr_fw_header *)(mem_unlock_fw->data +
135 hsbin_hdr->header_offset);
136
137 mem_unlock_ucode_header = (u32 *)(mem_unlock_fw->data +
138 fw_hdr->hdr_offset);
139 mem_unlock_ucode = (u32 *)(mem_unlock_fw->data +
140 hsbin_hdr->data_offset);
141
142 /* Patch Ucode singnatures */
143 if (acr_ucode_patch_sig(g, mem_unlock_ucode,
144 (u32 *)(mem_unlock_fw->data + fw_hdr->sig_prod_offset),
145 (u32 *)(mem_unlock_fw->data + fw_hdr->sig_dbg_offset),
146 (u32 *)(mem_unlock_fw->data + fw_hdr->patch_loc),
147 (u32 *)(mem_unlock_fw->data + fw_hdr->patch_sig)) < 0) {
148 nvgpu_err(g, "mem unlock patch signatures fail");
149 err = -EPERM;
150 goto exit;
151 }
152
153 /* Clear interrupts */
154 nvgpu_flcn_set_irq(&g->nvdec_flcn, false, 0x0, 0x0);
155
156 /* Copy Non Secure IMEM code */
157 nvgpu_flcn_copy_to_imem(&g->nvdec_flcn, 0,
158 (u8 *)&mem_unlock_ucode[
159 mem_unlock_ucode_header[OS_CODE_OFFSET] >> 2],
160 mem_unlock_ucode_header[OS_CODE_SIZE], 0, false,
161 GET_IMEM_TAG(mem_unlock_ucode_header[OS_CODE_OFFSET]));
162
163 /* Put secure code after non-secure block */
164 sec_imem_dest = GET_NEXT_BLOCK(mem_unlock_ucode_header[OS_CODE_SIZE]);
165
166 nvgpu_flcn_copy_to_imem(&g->nvdec_flcn, sec_imem_dest,
167 (u8 *)&mem_unlock_ucode[
168 mem_unlock_ucode_header[APP_0_CODE_OFFSET] >> 2],
169 mem_unlock_ucode_header[APP_0_CODE_SIZE], 0, true,
170 GET_IMEM_TAG(mem_unlock_ucode_header[APP_0_CODE_OFFSET]));
171
172 /* load DMEM: ensure that signatures are patched */
173 nvgpu_flcn_copy_to_dmem(&g->nvdec_flcn, 0, (u8 *)&mem_unlock_ucode[
174 mem_unlock_ucode_header[OS_DATA_OFFSET] >> 2],
175 mem_unlock_ucode_header[OS_DATA_SIZE], 0);
176
177 nvgpu_log_info(g, "nvdec sctl reg %x\n",
178 gk20a_readl(g, g->nvdec_flcn.flcn_base +
179 falcon_falcon_sctl_r()));
180
181 /* set BOOTVEC to start of non-secure code */
182 nvgpu_flcn_bootstrap(&g->nvdec_flcn, 0);
183
184 /* wait for complete & halt */
185 nvgpu_flcn_wait_for_halt(&g->nvdec_flcn, MEM_UNLOCK_TIMEOUT);
186
187 /* check mem unlock status */
188 val = nvgpu_flcn_mailbox_read(&g->nvdec_flcn, 0);
189 if (val) {
190 nvgpu_err(g, "memory unlock failed, err %x", val);
191 err = -1;
192 goto exit;
193 }
194
195 nvgpu_log_info(g, "nvdec sctl reg %x\n",
196 gk20a_readl(g, g->nvdec_flcn.flcn_base +
197 falcon_falcon_sctl_r()));
198
199exit:
200 if (mem_unlock_fw)
201 nvgpu_release_firmware(g, mem_unlock_fw);
202
203 nvgpu_log_fn(g, "done, status - %d", err);
204
205 return err;
206}
207
208int gv100_fb_init_nvlink(struct gk20a *g)
209{
210 u32 data;
211 u32 mask = g->nvlink.enabled_links;
212
213 /* Map enabled link to SYSMEM */
214 data = nvgpu_readl(g, fb_hshub_config0_r());
215 data = set_field(data, fb_hshub_config0_sysmem_nvlink_mask_m(),
216 fb_hshub_config0_sysmem_nvlink_mask_f(mask));
217 nvgpu_writel(g, fb_hshub_config0_r(), data);
218
219 return 0;
220}
221
222int gv100_fb_enable_nvlink(struct gk20a *g)
223{
224 u32 data;
225
226 nvgpu_log(g, gpu_dbg_nvlink|gpu_dbg_info, "enabling nvlink");
227
228 /* Enable nvlink for NISO FBHUB */
229 data = nvgpu_readl(g, fb_niso_cfg1_r());
230 data = set_field(data, fb_niso_cfg1_sysmem_nvlink_m(),
231 fb_niso_cfg1_sysmem_nvlink_enabled_f());
232 nvgpu_writel(g, fb_niso_cfg1_r(), data);
233
234 /* Setup atomics */
235 data = nvgpu_readl(g, fb_mmu_ctrl_r());
236 data = set_field(data, fb_mmu_ctrl_atomic_capability_mode_m(),
237 fb_mmu_ctrl_atomic_capability_mode_rmw_f());
238 nvgpu_writel(g, fb_mmu_ctrl_r(), data);
239
240 data = nvgpu_readl(g, fb_hsmmu_pri_mmu_ctrl_r());
241 data = set_field(data, fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_m(),
242 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_f());
243 nvgpu_writel(g, fb_hsmmu_pri_mmu_ctrl_r(), data);
244
245 data = nvgpu_readl(g, fb_fbhub_num_active_ltcs_r());
246 data = set_field(data, fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(),
247 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f());
248 nvgpu_writel(g, fb_fbhub_num_active_ltcs_r(), data);
249
250 data = nvgpu_readl(g, fb_hshub_num_active_ltcs_r());
251 data = set_field(data, fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(),
252 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f());
253 nvgpu_writel(g, fb_hshub_num_active_ltcs_r(), data);
254
255 return 0;
256}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 04:13:58 -0400