diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index defda1c3..9c83030f 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -1066,6 +1066,23 @@ static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | |||
1066 | tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); | 1066 | tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); |
1067 | } | 1067 | } |
1068 | 1068 | ||
1069 | static void gr_gp10b_get_access_map(struct gk20a *g, | ||
1070 | u32 **whitelist, int *num_entries) | ||
1071 | { | ||
1072 | static u32 wl_addr_gp10b[] = { | ||
1073 | /* this list must be sorted (low to high) */ | ||
1074 | 0x404468, /* gr_pri_mme_max_instructions */ | ||
1075 | 0x418800, /* gr_pri_gpcs_setup_debug */ | ||
1076 | 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */ | ||
1077 | 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */ | ||
1078 | 0x419e10, /* gr_pri_gpcs_tpcs_sm_dbgr_control0 */ | ||
1079 | 0x419f78, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */ | ||
1080 | }; | ||
1081 | |||
1082 | *whitelist = wl_addr_gp10b; | ||
1083 | *num_entries = ARRAY_SIZE(wl_addr_gp10b); | ||
1084 | } | ||
1085 | |||
1069 | void gp10b_init_gr(struct gpu_ops *gops) | 1086 | void gp10b_init_gr(struct gpu_ops *gops) |
1070 | { | 1087 | { |
1071 | gm20b_init_gr(gops); | 1088 | gm20b_init_gr(gops); |
@@ -1095,4 +1112,5 @@ void gp10b_init_gr(struct gpu_ops *gops) | |||
1095 | gops->gr.wait_empty = gr_gp10b_wait_empty; | 1112 | gops->gr.wait_empty = gr_gp10b_wait_empty; |
1096 | gops->gr.init_cyclestats = gr_gp10b_init_cyclestats; | 1113 | gops->gr.init_cyclestats = gr_gp10b_init_cyclestats; |
1097 | gops->gr.set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask; | 1114 | gops->gr.set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask; |
1115 | gops->gr.get_access_map = gr_gp10b_get_access_map; | ||
1098 | } | 1116 | } |