diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 38 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.h | 2 |
2 files changed, 23 insertions, 17 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index e7b2e70c..b5fdf2fd 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -222,26 +222,30 @@ static void pmu_handle_gr_param_msg(struct gk20a *g, struct pmu_msg *msg, | |||
222 | return; | 222 | return; |
223 | } | 223 | } |
224 | 224 | ||
225 | int gp10b_pg_gr_init(struct gk20a *g, u8 grfeaturemask) | 225 | int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) |
226 | { | 226 | { |
227 | struct pmu_gk20a *pmu = &g->pmu; | 227 | struct pmu_gk20a *pmu = &g->pmu; |
228 | struct pmu_cmd cmd; | 228 | struct pmu_cmd cmd; |
229 | u32 seq; | 229 | u32 seq; |
230 | 230 | ||
231 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | 231 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { |
232 | cmd.hdr.unit_id = PMU_UNIT_PG; | 232 | memset(&cmd, 0, sizeof(struct pmu_cmd)); |
233 | cmd.hdr.size = PMU_CMD_HDR_SIZE + | 233 | cmd.hdr.unit_id = PMU_UNIT_PG; |
234 | sizeof(struct pmu_pg_cmd_gr_init_param); | 234 | cmd.hdr.size = PMU_CMD_HDR_SIZE + |
235 | cmd.cmd.pg.gr_init_param.cmd_type = | 235 | sizeof(struct pmu_pg_cmd_gr_init_param); |
236 | PMU_PG_CMD_ID_PG_PARAM; | 236 | cmd.cmd.pg.gr_init_param.cmd_type = |
237 | cmd.cmd.pg.gr_init_param.sub_cmd_id = | 237 | PMU_PG_CMD_ID_PG_PARAM; |
238 | PMU_PG_PARAM_CMD_GR_INIT_PARAM; | 238 | cmd.cmd.pg.gr_init_param.sub_cmd_id = |
239 | cmd.cmd.pg.gr_init_param.featuremask = | 239 | PMU_PG_PARAM_CMD_GR_INIT_PARAM; |
240 | grfeaturemask; | 240 | cmd.cmd.pg.gr_init_param.featuremask = |
241 | 241 | PMU_PG_FEATURE_GR_POWER_GATING_ENABLED; | |
242 | gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM %x", grfeaturemask); | 242 | |
243 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 243 | gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM "); |
244 | pmu_handle_gr_param_msg, pmu, &seq, ~0); | 244 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
245 | pmu_handle_gr_param_msg, pmu, &seq, ~0); | ||
246 | |||
247 | } else | ||
248 | return -EINVAL; | ||
245 | 249 | ||
246 | return 0; | 250 | return 0; |
247 | } | 251 | } |
@@ -474,7 +478,9 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) | |||
474 | gops->pmu.fecsbootstrapdone = false; | 478 | gops->pmu.fecsbootstrapdone = false; |
475 | gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase; | 479 | gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase; |
476 | gops->pmu.pmu_elpg_statistics = gp10b_pmu_elpg_statistics; | 480 | gops->pmu.pmu_elpg_statistics = gp10b_pmu_elpg_statistics; |
477 | gops->pmu.pmu_pg_grinit_param = gp10b_pg_gr_init; | 481 | gops->pmu.pmu_pg_init_param = gp10b_pg_gr_init; |
482 | gops->pmu.pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list; | ||
483 | gops->pmu.pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list; | ||
478 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = | 484 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = |
479 | send_ecc_overide_en_dis_cmd; | 485 | send_ecc_overide_en_dis_cmd; |
480 | gops->pmu.reset = gk20a_pmu_reset; | 486 | gops->pmu.reset = gk20a_pmu_reset; |
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h index 18e7bdd3..30245554 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h | |||
@@ -18,7 +18,7 @@ | |||
18 | 18 | ||
19 | void gp10b_init_pmu_ops(struct gpu_ops *gops); | 19 | void gp10b_init_pmu_ops(struct gpu_ops *gops); |
20 | int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask); | 20 | int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask); |
21 | int gp10b_pg_gr_init(struct gk20a *g, u8 grfeaturemask); | 21 | int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id); |
22 | void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr); | 22 | void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr); |
23 | 23 | ||
24 | #endif /*__PMU_GP10B_H_*/ | 24 | #endif /*__PMU_GP10B_H_*/ |