diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 49ad3920..c94d580a 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B PMU | 2 | * GP10B PMU |
3 | * | 3 | * |
4 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -233,13 +233,15 @@ int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) | |||
233 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | 233 | memset(&cmd, 0, sizeof(struct pmu_cmd)); |
234 | cmd.hdr.unit_id = PMU_UNIT_PG; | 234 | cmd.hdr.unit_id = PMU_UNIT_PG; |
235 | cmd.hdr.size = PMU_CMD_HDR_SIZE + | 235 | cmd.hdr.size = PMU_CMD_HDR_SIZE + |
236 | sizeof(struct pmu_pg_cmd_gr_init_param); | 236 | sizeof(struct pmu_pg_cmd_gr_init_param_v2); |
237 | cmd.cmd.pg.gr_init_param.cmd_type = | 237 | cmd.cmd.pg.gr_init_param_v2.cmd_type = |
238 | PMU_PG_CMD_ID_PG_PARAM; | 238 | PMU_PG_CMD_ID_PG_PARAM; |
239 | cmd.cmd.pg.gr_init_param.sub_cmd_id = | 239 | cmd.cmd.pg.gr_init_param_v2.sub_cmd_id = |
240 | PMU_PG_PARAM_CMD_GR_INIT_PARAM; | 240 | PMU_PG_PARAM_CMD_GR_INIT_PARAM; |
241 | cmd.cmd.pg.gr_init_param.featuremask = | 241 | cmd.cmd.pg.gr_init_param_v2.featuremask = |
242 | NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING; | 242 | NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING; |
243 | cmd.cmd.pg.gr_init_param_v2.ldiv_slowdown_factor = | ||
244 | g->ldiv_slowdown_factor; | ||
243 | 245 | ||
244 | gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM "); | 246 | gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM "); |
245 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 247 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |