diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 19 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 20 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mc_gp10b.h | 11 |
3 files changed, 29 insertions, 21 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index d004cf3d..af1195ea 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include "gk20a/bus_gk20a.h" | 19 | #include "gk20a/bus_gk20a.h" |
20 | #include "gk20a/pramin_gk20a.h" | 20 | #include "gk20a/pramin_gk20a.h" |
21 | #include "gk20a/flcn_gk20a.h" | 21 | #include "gk20a/flcn_gk20a.h" |
22 | #include "gk20a/mc_gk20a.h" | ||
22 | 23 | ||
23 | #include "gp10b/gr_gp10b.h" | 24 | #include "gp10b/gr_gp10b.h" |
24 | #include "gp10b/fecs_trace_gp10b.h" | 25 | #include "gp10b/fecs_trace_gp10b.h" |
@@ -207,6 +208,22 @@ static const struct gpu_ops gp10b_ops = { | |||
207 | .pg_gr_load_gating_prod = | 208 | .pg_gr_load_gating_prod = |
208 | gr_gp10b_pg_gr_load_gating_prod, | 209 | gr_gp10b_pg_gr_load_gating_prod, |
209 | }, | 210 | }, |
211 | .mc = { | ||
212 | .intr_enable = mc_gp10b_intr_enable, | ||
213 | .intr_unit_config = mc_gp10b_intr_unit_config, | ||
214 | .isr_stall = mc_gp10b_isr_stall, | ||
215 | .intr_stall = mc_gp10b_intr_stall, | ||
216 | .intr_stall_pause = mc_gp10b_intr_stall_pause, | ||
217 | .intr_stall_resume = mc_gp10b_intr_stall_resume, | ||
218 | .intr_nonstall = mc_gp10b_intr_nonstall, | ||
219 | .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, | ||
220 | .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, | ||
221 | .enable = gk20a_mc_enable, | ||
222 | .disable = gk20a_mc_disable, | ||
223 | .reset = gk20a_mc_reset, | ||
224 | .boot_0 = gk20a_mc_boot_0, | ||
225 | .is_intr1_pending = mc_gp10b_is_intr1_pending, | ||
226 | }, | ||
210 | .cde = { | 227 | .cde = { |
211 | .get_program_numbers = gp10b_cde_get_program_numbers, | 228 | .get_program_numbers = gp10b_cde_get_program_numbers, |
212 | .need_scatter_buffer = gp10b_need_scatter_buffer, | 229 | .need_scatter_buffer = gp10b_need_scatter_buffer, |
@@ -227,6 +244,7 @@ int gp10b_init_hal(struct gk20a *g) | |||
227 | 244 | ||
228 | gops->ltc = gp10b_ops.ltc; | 245 | gops->ltc = gp10b_ops.ltc; |
229 | gops->clock_gating = gp10b_ops.clock_gating; | 246 | gops->clock_gating = gp10b_ops.clock_gating; |
247 | gops->mc = gp10b_ops.mc; | ||
230 | gops->cde = gp10b_ops.cde; | 248 | gops->cde = gp10b_ops.cde; |
231 | gops->falcon = gp10b_ops.falcon; | 249 | gops->falcon = gp10b_ops.falcon; |
232 | 250 | ||
@@ -274,7 +292,6 @@ int gp10b_init_hal(struct gk20a *g) | |||
274 | #endif | 292 | #endif |
275 | 293 | ||
276 | gk20a_init_bus(gops); | 294 | gk20a_init_bus(gops); |
277 | gp10b_init_mc(gops); | ||
278 | gp10b_init_priv_ring(gops); | 295 | gp10b_init_priv_ring(gops); |
279 | gp10b_init_gr(gops); | 296 | gp10b_init_gr(gops); |
280 | gp10b_init_fecs_trace_ops(gops); | 297 | gp10b_init_fecs_trace_ops(gops); |
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 39ad8f9b..5a1d5dcc 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c | |||
@@ -156,7 +156,7 @@ void mc_gp10b_intr_nonstall_resume(struct gk20a *g) | |||
156 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); | 156 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); |
157 | } | 157 | } |
158 | 158 | ||
159 | static bool mc_gp10b_is_intr1_pending(struct gk20a *g, | 159 | bool mc_gp10b_is_intr1_pending(struct gk20a *g, |
160 | enum nvgpu_unit unit, u32 mc_intr_1) | 160 | enum nvgpu_unit unit, u32 mc_intr_1) |
161 | { | 161 | { |
162 | u32 mask = 0; | 162 | u32 mask = 0; |
@@ -179,21 +179,3 @@ static bool mc_gp10b_is_intr1_pending(struct gk20a *g, | |||
179 | 179 | ||
180 | return is_pending; | 180 | return is_pending; |
181 | } | 181 | } |
182 | |||
183 | void gp10b_init_mc(struct gpu_ops *gops) | ||
184 | { | ||
185 | gops->mc.intr_enable = mc_gp10b_intr_enable; | ||
186 | gops->mc.intr_unit_config = mc_gp10b_intr_unit_config; | ||
187 | gops->mc.isr_stall = mc_gp10b_isr_stall; | ||
188 | gops->mc.intr_stall = mc_gp10b_intr_stall; | ||
189 | gops->mc.intr_stall_pause = mc_gp10b_intr_stall_pause; | ||
190 | gops->mc.intr_stall_resume = mc_gp10b_intr_stall_resume; | ||
191 | gops->mc.intr_nonstall = mc_gp10b_intr_nonstall; | ||
192 | gops->mc.intr_nonstall_pause = mc_gp10b_intr_nonstall_pause; | ||
193 | gops->mc.intr_nonstall_resume = mc_gp10b_intr_nonstall_resume; | ||
194 | gops->mc.enable = gk20a_mc_enable; | ||
195 | gops->mc.disable = gk20a_mc_disable; | ||
196 | gops->mc.reset = gk20a_mc_reset; | ||
197 | gops->mc.boot_0 = gk20a_mc_boot_0; | ||
198 | gops->mc.is_intr1_pending = mc_gp10b_is_intr1_pending; | ||
199 | } | ||
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h index ceba0b39..00e9dd1d 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h | |||
@@ -20,9 +20,18 @@ enum MC_INTERRUPT_REGLIST { | |||
20 | NVGPU_MC_INTR_NONSTALLING, | 20 | NVGPU_MC_INTR_NONSTALLING, |
21 | }; | 21 | }; |
22 | 22 | ||
23 | void gp10b_init_mc(struct gpu_ops *gops); | ||
24 | void mc_gp10b_intr_enable(struct gk20a *g); | 23 | void mc_gp10b_intr_enable(struct gk20a *g); |
25 | void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, | 24 | void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, |
26 | bool is_stalling, u32 mask); | 25 | bool is_stalling, u32 mask); |
27 | void mc_gp10b_isr_stall(struct gk20a *g); | 26 | void mc_gp10b_isr_stall(struct gk20a *g); |
27 | bool mc_gp10b_is_intr1_pending(struct gk20a *g, | ||
28 | enum nvgpu_unit unit, u32 mc_intr_1); | ||
29 | |||
30 | u32 mc_gp10b_intr_stall(struct gk20a *g); | ||
31 | void mc_gp10b_intr_stall_pause(struct gk20a *g); | ||
32 | void mc_gp10b_intr_stall_resume(struct gk20a *g); | ||
33 | u32 mc_gp10b_intr_nonstall(struct gk20a *g); | ||
34 | void mc_gp10b_intr_nonstall_pause(struct gk20a *g); | ||
35 | void mc_gp10b_intr_nonstall_resume(struct gk20a *g); | ||
36 | |||
28 | #endif | 37 | #endif |