summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gp10b
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r--drivers/gpu/nvgpu/gp10b/mc_gp10b.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
index 718869f6..b7a52349 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
@@ -71,14 +71,12 @@ void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
71void mc_gp10b_isr_stall(struct gk20a *g) 71void mc_gp10b_isr_stall(struct gk20a *g)
72{ 72{
73 u32 mc_intr_0; 73 u32 mc_intr_0;
74 int hw_irq_count;
75 74
76 u32 engine_id_idx; 75 u32 engine_id_idx;
77 u32 active_engine_id = 0; 76 u32 active_engine_id = 0;
78 u32 engine_enum = ENGINE_INVAL_GK20A; 77 u32 engine_enum = ENGINE_INVAL_GK20A;
79 78
80 mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); 79 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
81 hw_irq_count = atomic_read(&g->hw_irq_stall_count);
82 80
83 gk20a_dbg(gpu_dbg_intr, "stall intr 0x%08x\n", mc_intr_0); 81 gk20a_dbg(gpu_dbg_intr, "stall intr 0x%08x\n", mc_intr_0);
84 82
@@ -116,9 +114,6 @@ void mc_gp10b_isr_stall(struct gk20a *g)
116 if (mc_intr_0 & mc_intr_pbus_pending_f()) 114 if (mc_intr_0 & mc_intr_pbus_pending_f())
117 g->ops.bus.isr(g); 115 g->ops.bus.isr(g);
118 116
119 /* sync handled irq counter before re-enabling interrupts */
120 atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count);
121
122 gk20a_dbg(gpu_dbg_intr, "stall intr done 0x%08x\n", mc_intr_0); 117 gk20a_dbg(gpu_dbg_intr, "stall intr done 0x%08x\n", mc_intr_0);
123 118
124} 119}