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-rw-r--r--drivers/gpu/nvgpu/gp10b/ce_gp10b.h6
-rw-r--r--drivers/gpu/nvgpu/gp10b/ecc_gp10b.h6
-rw-r--r--drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h8
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h8
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.h6
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.h8
-rw-r--r--drivers/gpu/nvgpu/gp10b/pmu_gp10b.h6
-rw-r--r--drivers/gpu/nvgpu/gp10b/regops_gp10b.h6
8 files changed, 27 insertions, 27 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.h b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
index 525599af..4fa27d1e 100644
--- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
@@ -21,8 +21,8 @@
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE. 22 * DEALINGS IN THE SOFTWARE.
23 */ 23 */
24#ifndef __CE_GP10B_H__ 24#ifndef NVGPU_CE_GP10B_H
25#define __CE_GP10B_H__ 25#define NVGPU_CE_GP10B_H
26 26
27#include <nvgpu/types.h> 27#include <nvgpu/types.h>
28 28
@@ -31,4 +31,4 @@ struct gk20a;
31void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base); 31void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
32u32 gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base); 32u32 gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
33 33
34#endif /*__CE2_GP10B_H__*/ 34#endif /* NVGPU_CE_GP10B_H */
diff --git a/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h b/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h
index e5101db0..73145f9e 100644
--- a/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h
@@ -20,9 +20,9 @@
20 * DEALINGS IN THE SOFTWARE. 20 * DEALINGS IN THE SOFTWARE.
21 */ 21 */
22 22
23#ifndef __ECC_GP10B_H__ 23#ifndef NVGPU_ECC_GP10B_H
24#define __ECC_GP10B_H__ 24#define NVGPU_ECC_GP10B_H
25 25
26int gp10b_ecc_init(struct gk20a *g); 26int gp10b_ecc_init(struct gk20a *g);
27 27
28#endif 28#endif /* NVGPU_ECC_GP10B_H */
diff --git a/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h b/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h
index f192617c..0eda975b 100644
--- a/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GP10B GPU FECS traces 2 * GP10B GPU FECS traces
3 * 3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -22,11 +22,11 @@
22 * DEALINGS IN THE SOFTWARE. 22 * DEALINGS IN THE SOFTWARE.
23 */ 23 */
24 24
25#ifndef _NVGPU_FECS_TRACE_GP10B_H_ 25#ifndef NVGPU_FECS_TRACE_GP10B_H
26#define _NVGPU_FECS_TRACE_GP10B_H_ 26#define NVGPU_FECS_TRACE_GP10B_H
27 27
28struct gk20a; 28struct gk20a;
29 29
30int gp10b_fecs_trace_flush(struct gk20a *g); 30int gp10b_fecs_trace_flush(struct gk20a *g);
31 31
32#endif 32#endif /* NVGPU_FECS_TRACE_GP10B_H */
diff --git a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h
index b409b442..25cc027f 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GP10B Graphics Context 2 * GP10B Graphics Context
3 * 3 *
4 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -21,8 +21,8 @@
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE. 22 * DEALINGS IN THE SOFTWARE.
23 */ 23 */
24#ifndef __GR_CTX_GM10B_H__ 24#ifndef NVGPU_GR_CTX_GP10B_H
25#define __GR_CTX_GM10B_H__ 25#define NVGPU_GR_CTX_GP10B_H
26 26
27#include "gk20a/gr_ctx_gk20a.h" 27#include "gk20a/gr_ctx_gk20a.h"
28 28
@@ -32,4 +32,4 @@
32int gr_gp10b_get_netlist_name(struct gk20a *g, int index, char *name); 32int gr_gp10b_get_netlist_name(struct gk20a *g, int index, char *name);
33bool gr_gp10b_is_firmware_defined(void); 33bool gr_gp10b_is_firmware_defined(void);
34 34
35#endif /*__GR_CTX_GP10B_H__*/ 35#endif /* NVGPU_GR_CTX_GP10B_H */
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
index 31e1e6e9..2ae44e04 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
@@ -22,8 +22,8 @@
22 * DEALINGS IN THE SOFTWARE. 22 * DEALINGS IN THE SOFTWARE.
23 */ 23 */
24 24
25#ifndef _NVGPU_GR_GP10B_H_ 25#ifndef NVGPU_GR_GP10B_H
26#define _NVGPU_GR_GP10B_H_ 26#define NVGPU_GR_GP10B_H
27 27
28#include "gk20a/mm_gk20a.h" 28#include "gk20a/mm_gk20a.h"
29 29
@@ -156,4 +156,4 @@ unsigned long gr_gp10b_get_max_gfxp_wfi_timeout_count(struct gk20a *g);
156bool gr_gp10b_suspend_context(struct channel_gk20a *ch, 156bool gr_gp10b_suspend_context(struct channel_gk20a *ch,
157 bool *cilp_preempt_pending); 157 bool *cilp_preempt_pending);
158 158
159#endif 159#endif /* NVGPU_GR_GP10B_H */
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.h b/drivers/gpu/nvgpu/gp10b/hal_gp10b.h
index cf3c295d..6ba80b88 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GP10B Tegra HAL interface 2 * GP10B Tegra HAL interface
3 * 3 *
4 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -22,10 +22,10 @@
22 * DEALINGS IN THE SOFTWARE. 22 * DEALINGS IN THE SOFTWARE.
23 */ 23 */
24 24
25#ifndef _NVGPU_HAL_GP10B_H 25#ifndef NVGPU_HAL_GP10B_H
26#define _NVGPU_HAL_GP10B_H 26#define NVGPU_HAL_GP10B_H
27struct gk20a; 27struct gk20a;
28 28
29int gp10b_init_hal(struct gk20a *gops); 29int gp10b_init_hal(struct gk20a *gops);
30int gp10b_get_litter_value(struct gk20a *g, int value); 30int gp10b_get_litter_value(struct gk20a *g, int value);
31#endif 31#endif /* NVGPU_HAL_GP10B_H */
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
index 4fd4c7c4..9fe2ab7f 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
@@ -22,8 +22,8 @@
22 * DEALINGS IN THE SOFTWARE. 22 * DEALINGS IN THE SOFTWARE.
23 */ 23 */
24 24
25#ifndef __PMU_GP10B_H_ 25#ifndef NVGPU_PMU_GP10B_H
26#define __PMU_GP10B_H_ 26#define NVGPU_PMU_GP10B_H
27 27
28struct gk20a; 28struct gk20a;
29 29
@@ -38,4 +38,4 @@ int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask);
38int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id); 38int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id);
39void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr); 39void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr);
40 40
41#endif /*__PMU_GP10B_H_*/ 41#endif /* NVGPU_PMU_GP10B_H */
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h
index e8b9f325..9971b0d2 100644
--- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h
@@ -22,8 +22,8 @@
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE. 23 * DEALINGS IN THE SOFTWARE.
24 */ 24 */
25#ifndef __REGOPS_GP10B_H_ 25#ifndef NVGPU_REGOPS_GP10B_H
26#define __REGOPS_GP10B_H_ 26#define NVGPU_REGOPS_GP10B_H
27 27
28struct dbg_session_gk20a; 28struct dbg_session_gk20a;
29 29
@@ -41,4 +41,4 @@ const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void);
41u64 gp10b_get_qctl_whitelist_ranges_count(void); 41u64 gp10b_get_qctl_whitelist_ranges_count(void);
42int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s); 42int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
43 43
44#endif /* __REGOPS_GP10B_H_ */ 44#endif /* NVGPU_REGOPS_GP10B_H */