3 files changed, 5 insertions, 42 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 759d271e..740cb8b7 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -794,7 +794,8 @@ int gp10b_init_hal(struct gk20a *g)
                         gm20b_flcn_populate_bl_dmem_desc,
                 gops->pmu.update_lspmu_cmdline_args =
                         gm20b_update_lspmu_cmdline_args;
-                gops->pmu.setup_apertures = gm20b_setup_apertures;
+                gops->pmu.setup_apertures = gm20b_pmu_setup_apertures;
+                gops->pmu.secured_pmu_start = gm20b_secured_pmu_start;
 
                 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
                 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
@@ -806,6 +807,8 @@ int gp10b_init_hal(struct gk20a *g)
                 /* Inherit from gk20a */
                 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported,
                 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
+                gops->pmu.pmu_setup_hw_and_bootstrap =
+                        gm20b_ns_pmu_setup_hw_and_bootstrap;
                 gops->pmu.pmu_nsbootstrap = pmu_bootstrap,
 
                 gops->pmu.load_lsfalcon_ucode = NULL;
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
index 5c7d1523..d268ab88 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
@@ -304,45 +304,6 @@ void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr)
                                 0x0);
 }
 
-int gp10b_init_pmu_setup_hw1(struct gk20a *g)
-{
-        struct nvgpu_pmu *pmu = &g->pmu;
-        int err;
-
-        nvgpu_log_fn(g, " ");
-
-        nvgpu_mutex_acquire(&pmu->isr_mutex);
-        nvgpu_flcn_reset(pmu->flcn);
-        pmu->isr_enabled = true;
-        nvgpu_mutex_release(&pmu->isr_mutex);
-
-        /* setup apertures - virtual */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
-                pwr_fbif_transcfg_mem_type_virtual_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
-                pwr_fbif_transcfg_mem_type_virtual_f());
-
-        /* setup apertures - physical */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_local_fb_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_coherent_sysmem_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_noncoherent_sysmem_f());
-
-        err = g->ops.pmu.pmu_nsbootstrap(pmu);
-        if (err) {
-                return err;
-        }
-
-        nvgpu_log_fn(g, "done");
-        return 0;
-
-}
-
 bool gp10b_is_lazy_bootstrap(u32 falcon_id)
 {
         bool enable_status = false;
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
index 87c3ba79..4fd4c7c4 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
@@ -1,7 +1,7 @@
 /*
  * GP10B PMU
  *
- * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -31,7 +31,6 @@ struct gk20a;
 bool gp10b_is_lazy_bootstrap(u32 falcon_id);
 bool gp10b_is_priv_load(u32 falcon_id);
 bool gp10b_is_pmu_supported(struct gk20a *g);
-int gp10b_init_pmu_setup_hw1(struct gk20a *g);
 void gp10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
                 struct pmu_pg_stats_data *pg_stat_data);
 int gp10b_pmu_setup_elpg(struct gk20a *g);