diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ecc_gp10b.c | 106 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ecc_gp10b.h | 28 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 4 |
5 files changed, 151 insertions, 19 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/ecc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ecc_gp10b.c new file mode 100644 index 00000000..cf95c0d7 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/ecc_gp10b.c | |||
@@ -0,0 +1,106 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <nvgpu/ecc.h> | ||
24 | |||
25 | #include "gk20a/gk20a.h" | ||
26 | #include "gp10b/ecc_gp10b.h" | ||
27 | |||
28 | int gp10b_ecc_init(struct gk20a *g) | ||
29 | { | ||
30 | int err = 0; | ||
31 | |||
32 | err = NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_lrf_ecc_single_err_count); | ||
33 | if (err != 0) { | ||
34 | goto done; | ||
35 | } | ||
36 | err = NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_lrf_ecc_double_err_count); | ||
37 | if (err != 0) { | ||
38 | goto done; | ||
39 | } | ||
40 | |||
41 | err = NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_shm_ecc_sec_count); | ||
42 | if (err != 0) { | ||
43 | goto done; | ||
44 | } | ||
45 | err = NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_shm_ecc_sed_count); | ||
46 | if (err != 0) { | ||
47 | goto done; | ||
48 | } | ||
49 | err = NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_shm_ecc_ded_count); | ||
50 | if (err != 0) { | ||
51 | goto done; | ||
52 | } | ||
53 | |||
54 | err = NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_ecc_total_sec_pipe0_count); | ||
55 | if (err != 0) { | ||
56 | goto done; | ||
57 | } | ||
58 | err = NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_ecc_total_ded_pipe0_count); | ||
59 | if (err != 0) { | ||
60 | goto done; | ||
61 | } | ||
62 | |||
63 | err = NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_unique_ecc_sec_pipe0_count); | ||
64 | if (err != 0) { | ||
65 | goto done; | ||
66 | } | ||
67 | err = NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_unique_ecc_ded_pipe0_count); | ||
68 | if (err != 0) { | ||
69 | goto done; | ||
70 | } | ||
71 | |||
72 | err = NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_ecc_total_sec_pipe1_count); | ||
73 | if (err != 0) { | ||
74 | goto done; | ||
75 | } | ||
76 | err = NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_ecc_total_ded_pipe1_count); | ||
77 | if (err != 0) { | ||
78 | goto done; | ||
79 | } | ||
80 | |||
81 | err = NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_unique_ecc_sec_pipe1_count); | ||
82 | if (err != 0) { | ||
83 | goto done; | ||
84 | } | ||
85 | err = NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_unique_ecc_ded_pipe1_count); | ||
86 | if (err != 0) { | ||
87 | goto done; | ||
88 | } | ||
89 | |||
90 | err = NVGPU_ECC_COUNTER_INIT_PER_LTS(ecc_sec_count); | ||
91 | if (err != 0) { | ||
92 | goto done; | ||
93 | } | ||
94 | err = NVGPU_ECC_COUNTER_INIT_PER_LTS(ecc_ded_count); | ||
95 | if (err != 0) { | ||
96 | goto done; | ||
97 | } | ||
98 | |||
99 | done: | ||
100 | if (err != 0) { | ||
101 | nvgpu_err(g, "ecc counter allocate failed, err=%d", err); | ||
102 | nvgpu_ecc_free(g); | ||
103 | } | ||
104 | |||
105 | return err; | ||
106 | } | ||
diff --git a/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h b/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h new file mode 100644 index 00000000..e5101db0 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h | |||
@@ -0,0 +1,28 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef __ECC_GP10B_H__ | ||
24 | #define __ECC_GP10B_H__ | ||
25 | |||
26 | int gp10b_ecc_init(struct gk20a *g); | ||
27 | |||
28 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 16eddeca..17c4e8b7 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -176,7 +176,7 @@ int gr_gp10b_handle_sm_exception(struct gk20a *g, | |||
176 | lrf_ecc_ded_status, | 176 | lrf_ecc_ded_status, |
177 | &lrf_single_count_delta, | 177 | &lrf_single_count_delta, |
178 | lrf_double_count_delta); | 178 | lrf_double_count_delta); |
179 | g->ecc.gr.sm_lrf_single_err_count.counters[tpc] += | 179 | g->ecc.gr.sm_lrf_ecc_single_err_count[gpc][tpc].counter += |
180 | lrf_single_count_delta; | 180 | lrf_single_count_delta; |
181 | } | 181 | } |
182 | if (lrf_ecc_ded_status) { | 182 | if (lrf_ecc_ded_status) { |
@@ -188,7 +188,7 @@ int gr_gp10b_handle_sm_exception(struct gk20a *g, | |||
188 | lrf_ecc_ded_status, | 188 | lrf_ecc_ded_status, |
189 | &lrf_double_count_delta, | 189 | &lrf_double_count_delta, |
190 | lrf_single_count_delta); | 190 | lrf_single_count_delta); |
191 | g->ecc.gr.sm_lrf_double_err_count.counters[tpc] += | 191 | g->ecc.gr.sm_lrf_ecc_double_err_count[gpc][tpc].counter += |
192 | lrf_double_count_delta; | 192 | lrf_double_count_delta; |
193 | } | 193 | } |
194 | gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, | 194 | gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, |
@@ -213,9 +213,9 @@ int gr_gp10b_handle_sm_exception(struct gk20a *g, | |||
213 | ecc_stats_reg_val = | 213 | ecc_stats_reg_val = |
214 | gk20a_readl(g, | 214 | gk20a_readl(g, |
215 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); | 215 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); |
216 | g->ecc.gr.sm_shm_sec_count.counters[tpc] += | 216 | g->ecc.gr.sm_shm_ecc_sec_count[gpc][tpc].counter += |
217 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val); | 217 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val); |
218 | g->ecc.gr.sm_shm_sed_count.counters[tpc] += | 218 | g->ecc.gr.sm_shm_ecc_sed_count[gpc][tpc].counter += |
219 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val); | 219 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val); |
220 | ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() | | 220 | ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() | |
221 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m()); | 221 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m()); |
@@ -235,7 +235,7 @@ int gr_gp10b_handle_sm_exception(struct gk20a *g, | |||
235 | ecc_stats_reg_val = | 235 | ecc_stats_reg_val = |
236 | gk20a_readl(g, | 236 | gk20a_readl(g, |
237 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); | 237 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); |
238 | g->ecc.gr.sm_shm_ded_count.counters[tpc] += | 238 | g->ecc.gr.sm_shm_ecc_ded_count[gpc][tpc].counter += |
239 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val); | 239 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val); |
240 | ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m()); | 240 | ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m()); |
241 | gk20a_writel(g, | 241 | gk20a_writel(g, |
@@ -276,7 +276,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
276 | 276 | ||
277 | ecc_stats_reg_val = gk20a_readl(g, | 277 | ecc_stats_reg_val = gk20a_readl(g, |
278 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | 278 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); |
279 | g->ecc.gr.tex_total_sec_pipe0_count.counters[tpc] += | 279 | g->ecc.gr.tex_ecc_total_sec_pipe0_count[gpc][tpc].counter += |
280 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); | 280 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); |
281 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); | 281 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); |
282 | gk20a_writel(g, | 282 | gk20a_writel(g, |
@@ -285,7 +285,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
285 | 285 | ||
286 | ecc_stats_reg_val = gk20a_readl(g, | 286 | ecc_stats_reg_val = gk20a_readl(g, |
287 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | 287 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); |
288 | g->ecc.gr.tex_unique_sec_pipe0_count.counters[tpc] += | 288 | g->ecc.gr.tex_unique_ecc_sec_pipe0_count[gpc][tpc].counter += |
289 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); | 289 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); |
290 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); | 290 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); |
291 | gk20a_writel(g, | 291 | gk20a_writel(g, |
@@ -300,7 +300,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
300 | 300 | ||
301 | ecc_stats_reg_val = gk20a_readl(g, | 301 | ecc_stats_reg_val = gk20a_readl(g, |
302 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | 302 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); |
303 | g->ecc.gr.tex_total_sec_pipe1_count.counters[tpc] += | 303 | g->ecc.gr.tex_ecc_total_sec_pipe1_count[gpc][tpc].counter += |
304 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); | 304 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); |
305 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); | 305 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); |
306 | gk20a_writel(g, | 306 | gk20a_writel(g, |
@@ -309,7 +309,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
309 | 309 | ||
310 | ecc_stats_reg_val = gk20a_readl(g, | 310 | ecc_stats_reg_val = gk20a_readl(g, |
311 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | 311 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); |
312 | g->ecc.gr.tex_unique_sec_pipe1_count.counters[tpc] += | 312 | g->ecc.gr.tex_unique_ecc_sec_pipe1_count[gpc][tpc].counter += |
313 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); | 313 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); |
314 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); | 314 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); |
315 | gk20a_writel(g, | 315 | gk20a_writel(g, |
@@ -332,7 +332,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
332 | 332 | ||
333 | ecc_stats_reg_val = gk20a_readl(g, | 333 | ecc_stats_reg_val = gk20a_readl(g, |
334 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | 334 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); |
335 | g->ecc.gr.tex_total_ded_pipe0_count.counters[tpc] += | 335 | g->ecc.gr.tex_ecc_total_ded_pipe0_count[gpc][tpc].counter += |
336 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); | 336 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); |
337 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); | 337 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); |
338 | gk20a_writel(g, | 338 | gk20a_writel(g, |
@@ -341,7 +341,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
341 | 341 | ||
342 | ecc_stats_reg_val = gk20a_readl(g, | 342 | ecc_stats_reg_val = gk20a_readl(g, |
343 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | 343 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); |
344 | g->ecc.gr.tex_unique_ded_pipe0_count.counters[tpc] += | 344 | g->ecc.gr.tex_unique_ecc_ded_pipe0_count[gpc][tpc].counter += |
345 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); | 345 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); |
346 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); | 346 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); |
347 | gk20a_writel(g, | 347 | gk20a_writel(g, |
@@ -356,7 +356,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
356 | 356 | ||
357 | ecc_stats_reg_val = gk20a_readl(g, | 357 | ecc_stats_reg_val = gk20a_readl(g, |
358 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | 358 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); |
359 | g->ecc.gr.tex_total_ded_pipe1_count.counters[tpc] += | 359 | g->ecc.gr.tex_ecc_total_ded_pipe1_count[gpc][tpc].counter += |
360 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); | 360 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); |
361 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); | 361 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); |
362 | gk20a_writel(g, | 362 | gk20a_writel(g, |
@@ -365,7 +365,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
365 | 365 | ||
366 | ecc_stats_reg_val = gk20a_readl(g, | 366 | ecc_stats_reg_val = gk20a_readl(g, |
367 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | 367 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); |
368 | g->ecc.gr.tex_unique_ded_pipe1_count.counters[tpc] += | 368 | g->ecc.gr.tex_unique_ecc_ded_pipe1_count[gpc][tpc].counter += |
369 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); | 369 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); |
370 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); | 370 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); |
371 | gk20a_writel(g, | 371 | gk20a_writel(g, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 94adf727..d32f644d 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -56,6 +56,7 @@ | |||
56 | #include "gp10b/regops_gp10b.h" | 56 | #include "gp10b/regops_gp10b.h" |
57 | #include "gp10b/therm_gp10b.h" | 57 | #include "gp10b/therm_gp10b.h" |
58 | #include "gp10b/priv_ring_gp10b.h" | 58 | #include "gp10b/priv_ring_gp10b.h" |
59 | #include "gp10b/ecc_gp10b.h" | ||
59 | 60 | ||
60 | #include "gm20b/ltc_gm20b.h" | 61 | #include "gm20b/ltc_gm20b.h" |
61 | #include "gm20b/gr_gm20b.h" | 62 | #include "gm20b/gr_gm20b.h" |
@@ -339,11 +340,8 @@ static const struct gpu_ops gp10b_ops = { | |||
339 | .init_preemption_state = gr_gp10b_init_preemption_state, | 340 | .init_preemption_state = gr_gp10b_init_preemption_state, |
340 | .update_boosted_ctx = gr_gp10b_update_boosted_ctx, | 341 | .update_boosted_ctx = gr_gp10b_update_boosted_ctx, |
341 | .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, | 342 | .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, |
342 | #ifdef CONFIG_SYSFS | ||
343 | .create_gr_sysfs = gr_gp10b_create_sysfs, | ||
344 | .remove_gr_sysfs = gr_gp10b_remove_sysfs, | ||
345 | #endif | ||
346 | .set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode, | 343 | .set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode, |
344 | .init_ecc = gp10b_ecc_init, | ||
347 | .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data, | 345 | .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data, |
348 | .init_gfxp_wfi_timeout_count = | 346 | .init_gfxp_wfi_timeout_count = |
349 | gr_gp10b_init_gfxp_wfi_timeout_count, | 347 | gr_gp10b_init_gfxp_wfi_timeout_count, |
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index 1e5807d5..aeeda4a8 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | |||
@@ -249,7 +249,7 @@ void gp10b_ltc_isr(struct gk20a *g) | |||
249 | ecc_stats_reg_val = | 249 | ecc_stats_reg_val = |
250 | gk20a_readl(g, | 250 | gk20a_readl(g, |
251 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset); | 251 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset); |
252 | g->ecc.ltc.l2_sec_count.counters[ltc*g->ltc_count + slice] += | 252 | g->ecc.ltc.ecc_sec_count[ltc][slice].counter += |
253 | ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val); | 253 | ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val); |
254 | ecc_stats_reg_val &= | 254 | ecc_stats_reg_val &= |
255 | ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m()); | 255 | ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m()); |
@@ -268,7 +268,7 @@ void gp10b_ltc_isr(struct gk20a *g) | |||
268 | ecc_stats_reg_val = | 268 | ecc_stats_reg_val = |
269 | gk20a_readl(g, | 269 | gk20a_readl(g, |
270 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset); | 270 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset); |
271 | g->ecc.ltc.l2_ded_count.counters[ltc*g->ltc_count + slice] += | 271 | g->ecc.ltc.ecc_ded_count[ltc][slice].counter += |
272 | ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val); | 272 | ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val); |
273 | ecc_stats_reg_val &= | 273 | ecc_stats_reg_val &= |
274 | ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m()); | 274 | ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m()); |