diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 49 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mc_gp10b.h | 5 |
2 files changed, 22 insertions, 32 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 4a48d7fa..bfc7a3d4 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP20B master | 2 | * GP10B master |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -67,25 +67,6 @@ void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, | |||
67 | gk20a_writel(g, reg, mask); | 67 | gk20a_writel(g, reg, mask); |
68 | } | 68 | } |
69 | 69 | ||
70 | irqreturn_t mc_gp10b_isr_stall(struct gk20a *g) | ||
71 | { | ||
72 | u32 mc_intr_0; | ||
73 | |||
74 | if (!g->power_on) | ||
75 | return IRQ_NONE; | ||
76 | |||
77 | /* not from gpu when sharing irq with others */ | ||
78 | mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); | ||
79 | if (unlikely(!mc_intr_0)) | ||
80 | return IRQ_NONE; | ||
81 | |||
82 | gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); | ||
83 | |||
84 | atomic_inc(&g->hw_irq_stall_count); | ||
85 | |||
86 | return IRQ_WAKE_THREAD; | ||
87 | } | ||
88 | |||
89 | irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g) | 70 | irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g) |
90 | { | 71 | { |
91 | u32 mc_intr_1; | 72 | u32 mc_intr_1; |
@@ -117,7 +98,7 @@ irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g) | |||
117 | return IRQ_HANDLED; | 98 | return IRQ_HANDLED; |
118 | } | 99 | } |
119 | 100 | ||
120 | irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | 101 | void mc_gp10b_isr_stall(struct gk20a *g) |
121 | { | 102 | { |
122 | u32 mc_intr_0; | 103 | u32 mc_intr_0; |
123 | int hw_irq_count; | 104 | int hw_irq_count; |
@@ -126,8 +107,6 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | |||
126 | u32 active_engine_id = 0; | 107 | u32 active_engine_id = 0; |
127 | u32 engine_enum = ENGINE_INVAL_GK20A; | 108 | u32 engine_enum = ENGINE_INVAL_GK20A; |
128 | 109 | ||
129 | gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); | ||
130 | |||
131 | mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); | 110 | mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); |
132 | hw_irq_count = atomic_read(&g->hw_irq_stall_count); | 111 | hw_irq_count = atomic_read(&g->hw_irq_stall_count); |
133 | 112 | ||
@@ -172,12 +151,22 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | |||
172 | 151 | ||
173 | gk20a_dbg(gpu_dbg_intr, "stall intr done 0x%08x\n", mc_intr_0); | 152 | gk20a_dbg(gpu_dbg_intr, "stall intr done 0x%08x\n", mc_intr_0); |
174 | 153 | ||
175 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), | 154 | } |
176 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); | ||
177 | 155 | ||
178 | wake_up_all(&g->sw_irq_stall_last_handled_wq); | 156 | u32 mc_gp10b_intr_stall(struct gk20a *g) |
157 | { | ||
158 | return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING)); | ||
159 | } | ||
179 | 160 | ||
180 | return IRQ_HANDLED; | 161 | void mc_gp10b_intr_stall_pause(struct gk20a *g) |
162 | { | ||
163 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), 0xffffffff); | ||
164 | } | ||
165 | |||
166 | void mc_gp10b_intr_stall_resume(struct gk20a *g) | ||
167 | { | ||
168 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), | ||
169 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); | ||
181 | } | 170 | } |
182 | 171 | ||
183 | void gp10b_init_mc(struct gpu_ops *gops) | 172 | void gp10b_init_mc(struct gpu_ops *gops) |
@@ -185,8 +174,10 @@ void gp10b_init_mc(struct gpu_ops *gops) | |||
185 | gops->mc.intr_enable = mc_gp10b_intr_enable; | 174 | gops->mc.intr_enable = mc_gp10b_intr_enable; |
186 | gops->mc.intr_unit_config = mc_gp10b_intr_unit_config; | 175 | gops->mc.intr_unit_config = mc_gp10b_intr_unit_config; |
187 | gops->mc.isr_stall = mc_gp10b_isr_stall; | 176 | gops->mc.isr_stall = mc_gp10b_isr_stall; |
177 | gops->mc.intr_stall = mc_gp10b_intr_stall; | ||
178 | gops->mc.intr_stall_pause = mc_gp10b_intr_stall_pause; | ||
179 | gops->mc.intr_stall_resume = mc_gp10b_intr_stall_resume; | ||
188 | gops->mc.isr_nonstall = mc_gp10b_isr_nonstall; | 180 | gops->mc.isr_nonstall = mc_gp10b_isr_nonstall; |
189 | gops->mc.isr_thread_stall = mc_gp10b_intr_thread_stall; | ||
190 | gops->mc.isr_thread_nonstall = mc_gk20a_intr_thread_nonstall; | 181 | gops->mc.isr_thread_nonstall = mc_gk20a_intr_thread_nonstall; |
191 | gops->mc.isr_nonstall_cb = mc_gk20a_nonstall_cb; | 182 | gops->mc.isr_nonstall_cb = mc_gk20a_nonstall_cb; |
192 | gops->mc.enable = gk20a_mc_enable; | 183 | gops->mc.enable = gk20a_mc_enable; |
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h index b2ec4be4..31867a88 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -24,8 +24,7 @@ void gp10b_init_mc(struct gpu_ops *gops); | |||
24 | void mc_gp10b_intr_enable(struct gk20a *g); | 24 | void mc_gp10b_intr_enable(struct gk20a *g); |
25 | void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, | 25 | void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, |
26 | bool is_stalling, u32 mask); | 26 | bool is_stalling, u32 mask); |
27 | irqreturn_t mc_gp10b_isr_stall(struct gk20a *g); | 27 | void mc_gp10b_isr_stall(struct gk20a *g); |
28 | irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g); | 28 | irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g); |
29 | irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g); | ||
30 | irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g); | 29 | irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g); |
31 | #endif | 30 | #endif |