diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 |
3 files changed, 1 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 813b8891..a01cfbfa 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -1615,18 +1615,6 @@ int gr_gp10b_init_fs_state(struct gk20a *g) | |||
1615 | return gr_gm20b_init_fs_state(g); | 1615 | return gr_gm20b_init_fs_state(g); |
1616 | } | 1616 | } |
1617 | 1617 | ||
1618 | void gr_gp10b_init_cyclestats(struct gk20a *g) | ||
1619 | { | ||
1620 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
1621 | g->gpu_characteristics.flags |= | ||
1622 | NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS; | ||
1623 | g->gpu_characteristics.flags |= | ||
1624 | NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT; | ||
1625 | #else | ||
1626 | (void)g; | ||
1627 | #endif | ||
1628 | } | ||
1629 | |||
1630 | void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 1618 | void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
1631 | { | 1619 | { |
1632 | nvgpu_tegra_fuse_write_bypass(g, 0x1); | 1620 | nvgpu_tegra_fuse_write_bypass(g, 0x1); |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index 9ddc0375..a537f147 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h | |||
@@ -115,7 +115,6 @@ void gr_gp10b_commit_global_bundle_cb(struct gk20a *g, | |||
115 | struct channel_ctx_gk20a *ch_ctx, | 115 | struct channel_ctx_gk20a *ch_ctx, |
116 | u64 addr, u64 size, bool patch); | 116 | u64 addr, u64 size, bool patch); |
117 | int gr_gp10b_load_smid_config(struct gk20a *g); | 117 | int gr_gp10b_load_smid_config(struct gk20a *g); |
118 | void gr_gp10b_init_cyclestats(struct gk20a *g); | ||
119 | void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); | 118 | void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); |
120 | void gr_gp10b_get_access_map(struct gk20a *g, | 119 | void gr_gp10b_get_access_map(struct gk20a *g, |
121 | u32 **whitelist, int *num_entries); | 120 | u32 **whitelist, int *num_entries); |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 98e143f0..7b5cc2ac 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -243,7 +243,7 @@ static const struct gpu_ops gp10b_ops = { | |||
243 | .get_max_fbps_count = gr_gm20b_get_max_fbps_count, | 243 | .get_max_fbps_count = gr_gm20b_get_max_fbps_count, |
244 | .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info, | 244 | .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info, |
245 | .wait_empty = gr_gp10b_wait_empty, | 245 | .wait_empty = gr_gp10b_wait_empty, |
246 | .init_cyclestats = gr_gp10b_init_cyclestats, | 246 | .init_cyclestats = gr_gm20b_init_cyclestats, |
247 | .set_sm_debug_mode = gr_gk20a_set_sm_debug_mode, | 247 | .set_sm_debug_mode = gr_gk20a_set_sm_debug_mode, |
248 | .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, | 248 | .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, |
249 | .bpt_reg_info = gr_gm20b_bpt_reg_info, | 249 | .bpt_reg_info = gr_gm20b_bpt_reg_info, |