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-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c5
-rw-r--r--drivers/gpu/nvgpu/gp10b/ltc_gp10b.c3
-rw-r--r--drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c3
3 files changed, 7 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 133582cd..e2a931be 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -45,6 +45,7 @@
45#include "hal_gp10b.h" 45#include "hal_gp10b.h"
46 46
47#include <nvgpu/bug.h> 47#include <nvgpu/bug.h>
48#include <nvgpu/enabled.h>
48 49
49#include <nvgpu/hw/gp10b/hw_proj_gp10b.h> 50#include <nvgpu/hw/gp10b/hw_proj_gp10b.h>
50#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> 51#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
@@ -197,7 +198,7 @@ int gp10b_init_hal(struct gk20a *g)
197 gops->clock_gating = gp10b_ops.clock_gating; 198 gops->clock_gating = gp10b_ops.clock_gating;
198 gops->pmupstate = false; 199 gops->pmupstate = false;
199#ifdef CONFIG_TEGRA_ACR 200#ifdef CONFIG_TEGRA_ACR
200 if (g->is_fmodel) { 201 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
201 gops->privsecurity = 0; 202 gops->privsecurity = 0;
202 gops->securegpccs = 0; 203 gops->securegpccs = 0;
203 } else if (g->is_virtual) { 204 } else if (g->is_virtual) {
@@ -215,7 +216,7 @@ int gp10b_init_hal(struct gk20a *g)
215 } 216 }
216 } 217 }
217#else 218#else
218 if (g->is_fmodel) { 219 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
219 gk20a_dbg_info("running simulator with PRIV security disabled"); 220 gk20a_dbg_info("running simulator with PRIV security disabled");
220 gops->privsecurity = 0; 221 gops->privsecurity = 0;
221 gops->securegpccs = 0; 222 gops->securegpccs = 0;
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
index 165e93fe..5cf5a644 100644
--- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
@@ -19,6 +19,7 @@
19#include "gm20b/ltc_gm20b.h" 19#include "gm20b/ltc_gm20b.h"
20 20
21#include <nvgpu/log.h> 21#include <nvgpu/log.h>
22#include <nvgpu/enabled.h>
22 23
23#include <nvgpu/hw/gp10b/hw_mc_gp10b.h> 24#include <nvgpu/hw/gp10b/hw_mc_gp10b.h>
24#include <nvgpu/hw/gp10b/hw_ltc_gp10b.h> 25#include <nvgpu/hw/gp10b/hw_ltc_gp10b.h>
@@ -102,7 +103,7 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
102 gk20a_dbg_info("gobs_per_comptagline_per_slice: %d", 103 gk20a_dbg_info("gobs_per_comptagline_per_slice: %d",
103 gobs_per_comptagline_per_slice); 104 gobs_per_comptagline_per_slice);
104 105
105 if (g->is_fmodel) 106 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
106 err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); 107 err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size);
107 else 108 else
108 err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); 109 err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size);
diff --git a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c
index 7cdbec5e..8aaa7bff 100644
--- a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c
@@ -20,6 +20,7 @@
20 20
21#include <nvgpu/log.h> 21#include <nvgpu/log.h>
22#include <nvgpu/timers.h> 22#include <nvgpu/timers.h>
23#include <nvgpu/enabled.h>
23 24
24#include <nvgpu/hw/gp10b/hw_mc_gp10b.h> 25#include <nvgpu/hw/gp10b/hw_mc_gp10b.h>
25#include <nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h> 26#include <nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h>
@@ -34,7 +35,7 @@ static void gp10b_priv_ring_isr(struct gk20a *g)
34 u32 gpc; 35 u32 gpc;
35 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); 36 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
36 37
37 if (g->is_fmodel) 38 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
38 return; 39 return;
39 40
40 status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); 41 status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r());