diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ce_gp10b.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 23 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 186 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 37 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 17 |
7 files changed, 178 insertions, 97 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c index 76179b78..0c07c069 100644 --- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c | |||
@@ -51,11 +51,13 @@ void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | |||
51 | nvgpu_log(g, gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id); | 51 | nvgpu_log(g, gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id); |
52 | 52 | ||
53 | /* clear blocking interrupts: they exibit broken behavior */ | 53 | /* clear blocking interrupts: they exibit broken behavior */ |
54 | if (ce_intr & ce_intr_status_blockpipe_pending_f()) | 54 | if (ce_intr & ce_intr_status_blockpipe_pending_f()) { |
55 | clear_intr |= ce_blockpipe_isr(g, ce_intr); | 55 | clear_intr |= ce_blockpipe_isr(g, ce_intr); |
56 | } | ||
56 | 57 | ||
57 | if (ce_intr & ce_intr_status_launcherr_pending_f()) | 58 | if (ce_intr & ce_intr_status_launcherr_pending_f()) { |
58 | clear_intr |= ce_launcherr_isr(g, ce_intr); | 59 | clear_intr |= ce_launcherr_isr(g, ce_intr); |
60 | } | ||
59 | 61 | ||
60 | gk20a_writel(g, ce_intr_status_r(inst_id), clear_intr); | 62 | gk20a_writel(g, ce_intr_status_r(inst_id), clear_intr); |
61 | return; | 63 | return; |
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index 011d5f17..c10e389c 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | |||
@@ -150,8 +150,9 @@ int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c) | |||
150 | v = nvgpu_mem_rd32(c->g, &c->inst_block, | 150 | v = nvgpu_mem_rd32(c->g, &c->inst_block, |
151 | ram_fc_allowed_syncpoints_w()); | 151 | ram_fc_allowed_syncpoints_w()); |
152 | old_syncpt = pbdma_allowed_syncpoints_0_index_v(v); | 152 | old_syncpt = pbdma_allowed_syncpoints_0_index_v(v); |
153 | if (c->sync) | 153 | if (c->sync) { |
154 | new_syncpt = c->sync->syncpt_id(c->sync); | 154 | new_syncpt = c->sync->syncpt_id(c->sync); |
155 | } | ||
155 | 156 | ||
156 | if (new_syncpt && new_syncpt != old_syncpt) { | 157 | if (new_syncpt && new_syncpt != old_syncpt) { |
157 | /* disable channel */ | 158 | /* disable channel */ |
@@ -185,9 +186,9 @@ int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type, | |||
185 | int ret = ENGINE_INVAL_GK20A; | 186 | int ret = ENGINE_INVAL_GK20A; |
186 | 187 | ||
187 | nvgpu_log_info(g, "engine type %d", engine_type); | 188 | nvgpu_log_info(g, "engine type %d", engine_type); |
188 | if (engine_type == top_device_info_type_enum_graphics_v()) | 189 | if (engine_type == top_device_info_type_enum_graphics_v()) { |
189 | ret = ENGINE_GR_GK20A; | 190 | ret = ENGINE_GR_GK20A; |
190 | else if (engine_type == top_device_info_type_enum_lce_v()) { | 191 | } else if (engine_type == top_device_info_type_enum_lce_v()) { |
191 | /* Default assumptions - all the CE engine have separate runlist */ | 192 | /* Default assumptions - all the CE engine have separate runlist */ |
192 | ret = ENGINE_ASYNC_CE_GK20A; | 193 | ret = ENGINE_ASYNC_CE_GK20A; |
193 | } | 194 | } |
@@ -200,8 +201,9 @@ void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry, | |||
200 | { | 201 | { |
201 | if (top_device_info_data_type_v(table_entry) == | 202 | if (top_device_info_data_type_v(table_entry) == |
202 | top_device_info_data_type_enum2_v()) { | 203 | top_device_info_data_type_enum2_v()) { |
203 | if (inst_id) | 204 | if (inst_id) { |
204 | *inst_id = top_device_info_data_inst_id_v(table_entry); | 205 | *inst_id = top_device_info_data_inst_id_v(table_entry); |
206 | } | ||
205 | if (pri_base) { | 207 | if (pri_base) { |
206 | *pri_base = | 208 | *pri_base = |
207 | (top_device_info_data_pri_base_v(table_entry) | 209 | (top_device_info_data_pri_base_v(table_entry) |
@@ -214,9 +216,10 @@ void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry, | |||
214 | g->ops.fifo.device_info_fault_id(table_entry); | 216 | g->ops.fifo.device_info_fault_id(table_entry); |
215 | nvgpu_log_info(g, "device info: fault_id: %d", *fault_id); | 217 | nvgpu_log_info(g, "device info: fault_id: %d", *fault_id); |
216 | } | 218 | } |
217 | } else | 219 | } else { |
218 | nvgpu_err(g, "unknown device_info_data %d", | 220 | nvgpu_err(g, "unknown device_info_data %d", |
219 | top_device_info_data_type_v(table_entry)); | 221 | top_device_info_data_type_v(table_entry)); |
222 | } | ||
220 | } | 223 | } |
221 | 224 | ||
222 | void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) | 225 | void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) |
@@ -330,21 +333,23 @@ static const char * const gp10b_hub_client_descs[] = { | |||
330 | /* fill in mmu fault desc */ | 333 | /* fill in mmu fault desc */ |
331 | void gp10b_fifo_get_mmu_fault_desc(struct mmu_fault_info *mmfault) | 334 | void gp10b_fifo_get_mmu_fault_desc(struct mmu_fault_info *mmfault) |
332 | { | 335 | { |
333 | if (mmfault->fault_type >= ARRAY_SIZE(gp10b_fault_type_descs)) | 336 | if (mmfault->fault_type >= ARRAY_SIZE(gp10b_fault_type_descs)) { |
334 | WARN_ON(mmfault->fault_type >= | 337 | WARN_ON(mmfault->fault_type >= |
335 | ARRAY_SIZE(gp10b_fault_type_descs)); | 338 | ARRAY_SIZE(gp10b_fault_type_descs)); |
336 | else | 339 | } else { |
337 | mmfault->fault_type_desc = | 340 | mmfault->fault_type_desc = |
338 | gp10b_fault_type_descs[mmfault->fault_type]; | 341 | gp10b_fault_type_descs[mmfault->fault_type]; |
342 | } | ||
339 | } | 343 | } |
340 | 344 | ||
341 | /* fill in mmu fault client description */ | 345 | /* fill in mmu fault client description */ |
342 | void gp10b_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmfault) | 346 | void gp10b_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmfault) |
343 | { | 347 | { |
344 | if (mmfault->client_id >= ARRAY_SIZE(gp10b_hub_client_descs)) | 348 | if (mmfault->client_id >= ARRAY_SIZE(gp10b_hub_client_descs)) { |
345 | WARN_ON(mmfault->client_id >= | 349 | WARN_ON(mmfault->client_id >= |
346 | ARRAY_SIZE(gp10b_hub_client_descs)); | 350 | ARRAY_SIZE(gp10b_hub_client_descs)); |
347 | else | 351 | } else { |
348 | mmfault->client_id_desc = | 352 | mmfault->client_id_desc = |
349 | gp10b_hub_client_descs[mmfault->client_id]; | 353 | gp10b_hub_client_descs[mmfault->client_id]; |
354 | } | ||
350 | } | 355 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index a4e8ecde..f5377bc3 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -76,18 +76,20 @@ bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num) | |||
76 | 76 | ||
77 | bool gr_gp10b_is_valid_gfx_class(struct gk20a *g, u32 class_num) | 77 | bool gr_gp10b_is_valid_gfx_class(struct gk20a *g, u32 class_num) |
78 | { | 78 | { |
79 | if (class_num == PASCAL_A || class_num == MAXWELL_B) | 79 | if (class_num == PASCAL_A || class_num == MAXWELL_B) { |
80 | return true; | 80 | return true; |
81 | else | 81 | } else { |
82 | return false; | 82 | return false; |
83 | } | ||
83 | } | 84 | } |
84 | 85 | ||
85 | bool gr_gp10b_is_valid_compute_class(struct gk20a *g, u32 class_num) | 86 | bool gr_gp10b_is_valid_compute_class(struct gk20a *g, u32 class_num) |
86 | { | 87 | { |
87 | if (class_num == PASCAL_COMPUTE_A || class_num == MAXWELL_COMPUTE_B) | 88 | if (class_num == PASCAL_COMPUTE_A || class_num == MAXWELL_COMPUTE_B) { |
88 | return true; | 89 | return true; |
89 | else | 90 | } else { |
90 | return false; | 91 | return false; |
92 | } | ||
91 | } | 93 | } |
92 | 94 | ||
93 | 95 | ||
@@ -120,10 +122,11 @@ static void gr_gp10b_sm_lrf_ecc_overcount_war(int single_err, | |||
120 | hweight32(sed_status & ded_status); | 122 | hweight32(sed_status & ded_status); |
121 | } | 123 | } |
122 | 124 | ||
123 | if (*count_to_adjust > over_count) | 125 | if (*count_to_adjust > over_count) { |
124 | *count_to_adjust -= over_count; | 126 | *count_to_adjust -= over_count; |
125 | else | 127 | } else { |
126 | *count_to_adjust = 0; | 128 | *count_to_adjust = 0; |
129 | } | ||
127 | } | 130 | } |
128 | 131 | ||
129 | int gr_gp10b_handle_sm_exception(struct gk20a *g, | 132 | int gr_gp10b_handle_sm_exception(struct gk20a *g, |
@@ -407,8 +410,9 @@ int gr_gp10b_commit_global_cb_manager(struct gk20a *g, | |||
407 | nvgpu_log_fn(g, " "); | 410 | nvgpu_log_fn(g, " "); |
408 | 411 | ||
409 | tsg = tsg_gk20a_from_ch(c); | 412 | tsg = tsg_gk20a_from_ch(c); |
410 | if (!tsg) | 413 | if (!tsg) { |
411 | return -EINVAL; | 414 | return -EINVAL; |
415 | } | ||
412 | 416 | ||
413 | gr_ctx = &tsg->gr_ctx; | 417 | gr_ctx = &tsg->gr_ctx; |
414 | 418 | ||
@@ -740,8 +744,9 @@ void gr_gp10b_cb_size_default(struct gk20a *g) | |||
740 | { | 744 | { |
741 | struct gr_gk20a *gr = &g->gr; | 745 | struct gr_gk20a *gr = &g->gr; |
742 | 746 | ||
743 | if (!gr->attrib_cb_default_size) | 747 | if (!gr->attrib_cb_default_size) { |
744 | gr->attrib_cb_default_size = 0x800; | 748 | gr->attrib_cb_default_size = 0x800; |
749 | } | ||
745 | gr->alpha_cb_default_size = | 750 | gr->alpha_cb_default_size = |
746 | gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); | 751 | gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); |
747 | gr->attrib_cb_gfxp_default_size = | 752 | gr->attrib_cb_gfxp_default_size = |
@@ -765,8 +770,9 @@ void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) | |||
765 | 770 | ||
766 | nvgpu_log_fn(g, " "); | 771 | nvgpu_log_fn(g, " "); |
767 | 772 | ||
768 | if (alpha_cb_size > gr->alpha_cb_size) | 773 | if (alpha_cb_size > gr->alpha_cb_size) { |
769 | alpha_cb_size = gr->alpha_cb_size; | 774 | alpha_cb_size = gr->alpha_cb_size; |
775 | } | ||
770 | 776 | ||
771 | gk20a_writel(g, gr_ds_tga_constraintlogic_alpha_r(), | 777 | gk20a_writel(g, gr_ds_tga_constraintlogic_alpha_r(), |
772 | (gk20a_readl(g, gr_ds_tga_constraintlogic_alpha_r()) & | 778 | (gk20a_readl(g, gr_ds_tga_constraintlogic_alpha_r()) & |
@@ -818,8 +824,9 @@ void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data) | |||
818 | 824 | ||
819 | nvgpu_log_fn(g, " "); | 825 | nvgpu_log_fn(g, " "); |
820 | 826 | ||
821 | if (cb_size_steady > gr->attrib_cb_size) | 827 | if (cb_size_steady > gr->attrib_cb_size) { |
822 | cb_size_steady = gr->attrib_cb_size; | 828 | cb_size_steady = gr->attrib_cb_size; |
829 | } | ||
823 | if (gk20a_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r()) != | 830 | if (gk20a_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r()) != |
824 | gk20a_readl(g, | 831 | gk20a_readl(g, |
825 | gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r())) { | 832 | gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r())) { |
@@ -889,8 +896,9 @@ int gr_gp10b_init_ctx_state(struct gk20a *g) | |||
889 | nvgpu_log_fn(g, " "); | 896 | nvgpu_log_fn(g, " "); |
890 | 897 | ||
891 | err = gr_gk20a_init_ctx_state(g); | 898 | err = gr_gk20a_init_ctx_state(g); |
892 | if (err) | 899 | if (err) { |
893 | return err; | 900 | return err; |
901 | } | ||
894 | 902 | ||
895 | if (!g->gr.ctx_vars.preempt_image_size) { | 903 | if (!g->gr.ctx_vars.preempt_image_size) { |
896 | op.method.addr = | 904 | op.method.addr = |
@@ -920,8 +928,9 @@ int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size, | |||
920 | nvgpu_log_fn(g, " "); | 928 | nvgpu_log_fn(g, " "); |
921 | 929 | ||
922 | err = nvgpu_dma_alloc_sys(vm->mm->g, size, mem); | 930 | err = nvgpu_dma_alloc_sys(vm->mm->g, size, mem); |
923 | if (err) | 931 | if (err) { |
924 | return err; | 932 | return err; |
933 | } | ||
925 | 934 | ||
926 | mem->gpu_va = nvgpu_gmmu_map(vm, | 935 | mem->gpu_va = nvgpu_gmmu_map(vm, |
927 | mem, | 936 | mem, |
@@ -952,29 +961,35 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, | |||
952 | int err = 0; | 961 | int err = 0; |
953 | 962 | ||
954 | if (g->ops.gr.is_valid_gfx_class(g, class) && | 963 | if (g->ops.gr.is_valid_gfx_class(g, class) && |
955 | g->gr.ctx_vars.force_preemption_gfxp) | 964 | g->gr.ctx_vars.force_preemption_gfxp) { |
956 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; | 965 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; |
966 | } | ||
957 | 967 | ||
958 | if (g->ops.gr.is_valid_compute_class(g, class) && | 968 | if (g->ops.gr.is_valid_compute_class(g, class) && |
959 | g->gr.ctx_vars.force_preemption_cilp) | 969 | g->gr.ctx_vars.force_preemption_cilp) { |
960 | compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; | 970 | compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; |
971 | } | ||
961 | 972 | ||
962 | /* check for invalid combinations */ | 973 | /* check for invalid combinations */ |
963 | if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0)) | 974 | if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0)) { |
964 | return -EINVAL; | 975 | return -EINVAL; |
976 | } | ||
965 | 977 | ||
966 | if ((graphics_preempt_mode == NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) && | 978 | if ((graphics_preempt_mode == NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) && |
967 | (compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CILP)) | 979 | (compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CILP)) { |
968 | return -EINVAL; | 980 | return -EINVAL; |
981 | } | ||
969 | 982 | ||
970 | /* Do not allow lower preemption modes than current ones */ | 983 | /* Do not allow lower preemption modes than current ones */ |
971 | if (graphics_preempt_mode && | 984 | if (graphics_preempt_mode && |
972 | (graphics_preempt_mode < gr_ctx->graphics_preempt_mode)) | 985 | (graphics_preempt_mode < gr_ctx->graphics_preempt_mode)) { |
973 | return -EINVAL; | 986 | return -EINVAL; |
987 | } | ||
974 | 988 | ||
975 | if (compute_preempt_mode && | 989 | if (compute_preempt_mode && |
976 | (compute_preempt_mode < gr_ctx->compute_preempt_mode)) | 990 | (compute_preempt_mode < gr_ctx->compute_preempt_mode)) { |
977 | return -EINVAL; | 991 | return -EINVAL; |
992 | } | ||
978 | 993 | ||
979 | /* set preemption modes */ | 994 | /* set preemption modes */ |
980 | switch (graphics_preempt_mode) { | 995 | switch (graphics_preempt_mode) { |
@@ -1079,15 +1094,18 @@ int gr_gp10b_alloc_gr_ctx(struct gk20a *g, | |||
1079 | nvgpu_log_fn(g, " "); | 1094 | nvgpu_log_fn(g, " "); |
1080 | 1095 | ||
1081 | err = gr_gk20a_alloc_gr_ctx(g, gr_ctx, vm, class, flags); | 1096 | err = gr_gk20a_alloc_gr_ctx(g, gr_ctx, vm, class, flags); |
1082 | if (err) | 1097 | if (err) { |
1083 | return err; | 1098 | return err; |
1099 | } | ||
1084 | 1100 | ||
1085 | gr_ctx->ctx_id_valid = false; | 1101 | gr_ctx->ctx_id_valid = false; |
1086 | 1102 | ||
1087 | if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_GFXP) | 1103 | if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_GFXP) { |
1088 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; | 1104 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; |
1089 | if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_CILP) | 1105 | } |
1106 | if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_CILP) { | ||
1090 | compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; | 1107 | compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; |
1108 | } | ||
1091 | 1109 | ||
1092 | if (graphics_preempt_mode || compute_preempt_mode) { | 1110 | if (graphics_preempt_mode || compute_preempt_mode) { |
1093 | if (g->ops.gr.set_ctxsw_preemption_mode) { | 1111 | if (g->ops.gr.set_ctxsw_preemption_mode) { |
@@ -1097,8 +1115,9 @@ int gr_gp10b_alloc_gr_ctx(struct gk20a *g, | |||
1097 | nvgpu_err(g, "set_ctxsw_preemption_mode failed"); | 1115 | nvgpu_err(g, "set_ctxsw_preemption_mode failed"); |
1098 | goto fail_free_gk20a_ctx; | 1116 | goto fail_free_gk20a_ctx; |
1099 | } | 1117 | } |
1100 | } else | 1118 | } else { |
1101 | goto fail_free_gk20a_ctx; | 1119 | goto fail_free_gk20a_ctx; |
1120 | } | ||
1102 | } | 1121 | } |
1103 | 1122 | ||
1104 | nvgpu_log_fn(g, "done"); | 1123 | nvgpu_log_fn(g, "done"); |
@@ -1177,8 +1196,9 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
1177 | nvgpu_log_fn(g, " "); | 1196 | nvgpu_log_fn(g, " "); |
1178 | 1197 | ||
1179 | tsg = tsg_gk20a_from_ch(c); | 1198 | tsg = tsg_gk20a_from_ch(c); |
1180 | if (!tsg) | 1199 | if (!tsg) { |
1181 | return; | 1200 | return; |
1201 | } | ||
1182 | 1202 | ||
1183 | gr_ctx = &tsg->gr_ctx; | 1203 | gr_ctx = &tsg->gr_ctx; |
1184 | 1204 | ||
@@ -1209,12 +1229,13 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
1209 | u32 cbes_reserve; | 1229 | u32 cbes_reserve; |
1210 | 1230 | ||
1211 | if (g->ops.gr.set_preemption_buffer_va) { | 1231 | if (g->ops.gr.set_preemption_buffer_va) { |
1212 | if (ctxheader->gpu_va) | 1232 | if (ctxheader->gpu_va) { |
1213 | g->ops.gr.set_preemption_buffer_va(g, ctxheader, | 1233 | g->ops.gr.set_preemption_buffer_va(g, ctxheader, |
1214 | gr_ctx->preempt_ctxsw_buffer.gpu_va); | 1234 | gr_ctx->preempt_ctxsw_buffer.gpu_va); |
1215 | else | 1235 | } else { |
1216 | g->ops.gr.set_preemption_buffer_va(g, mem, | 1236 | g->ops.gr.set_preemption_buffer_va(g, mem, |
1217 | gr_ctx->preempt_ctxsw_buffer.gpu_va); | 1237 | gr_ctx->preempt_ctxsw_buffer.gpu_va); |
1238 | } | ||
1218 | } | 1239 | } |
1219 | 1240 | ||
1220 | err = gr_gk20a_ctx_patch_write_begin(g, gr_ctx, true); | 1241 | err = gr_gk20a_ctx_patch_write_begin(g, gr_ctx, true); |
@@ -1237,8 +1258,9 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
1237 | (32 - gr_scc_pagepool_base_addr_39_8_align_bits_v())); | 1258 | (32 - gr_scc_pagepool_base_addr_39_8_align_bits_v())); |
1238 | size = gr_ctx->pagepool_ctxsw_buffer.size; | 1259 | size = gr_ctx->pagepool_ctxsw_buffer.size; |
1239 | 1260 | ||
1240 | if (size == g->ops.gr.pagepool_default_size(g)) | 1261 | if (size == g->ops.gr.pagepool_default_size(g)) { |
1241 | size = gr_scc_pagepool_total_pages_hwmax_v(); | 1262 | size = gr_scc_pagepool_total_pages_hwmax_v(); |
1263 | } | ||
1242 | 1264 | ||
1243 | g->ops.gr.commit_global_pagepool(g, gr_ctx, addr, size, true); | 1265 | g->ops.gr.commit_global_pagepool(g, gr_ctx, addr, size, true); |
1244 | 1266 | ||
@@ -1325,9 +1347,10 @@ int gr_gp10b_dump_gr_status_regs(struct gk20a *g, | |||
1325 | gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity3_r())); | 1347 | gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity3_r())); |
1326 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n", | 1348 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n", |
1327 | gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r())); | 1349 | gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r())); |
1328 | if (gr->gpc_tpc_count && gr->gpc_tpc_count[0] == 2) | 1350 | if (gr->gpc_tpc_count && gr->gpc_tpc_count[0] == 2) { |
1329 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", | 1351 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", |
1330 | gk20a_readl(g, gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r())); | 1352 | gk20a_readl(g, gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r())); |
1353 | } | ||
1331 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", | 1354 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", |
1332 | gk20a_readl(g, gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r())); | 1355 | gk20a_readl(g, gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r())); |
1333 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0: 0x%x\n", | 1356 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0: 0x%x\n", |
@@ -1340,9 +1363,10 @@ int gr_gp10b_dump_gr_status_regs(struct gk20a *g, | |||
1340 | gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_3_r())); | 1363 | gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_3_r())); |
1341 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n", | 1364 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n", |
1342 | gk20a_readl(g, gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r())); | 1365 | gk20a_readl(g, gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r())); |
1343 | if (gr->gpc_tpc_count && gr->gpc_tpc_count[0] == 2) | 1366 | if (gr->gpc_tpc_count && gr->gpc_tpc_count[0] == 2) { |
1344 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", | 1367 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", |
1345 | gk20a_readl(g, gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r())); | 1368 | gk20a_readl(g, gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r())); |
1369 | } | ||
1346 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", | 1370 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", |
1347 | gk20a_readl(g, gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r())); | 1371 | gk20a_readl(g, gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r())); |
1348 | gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0: 0x%x\n", | 1372 | gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0: 0x%x\n", |
@@ -1415,8 +1439,9 @@ static bool gr_activity_empty_or_preempted(u32 val) | |||
1415 | while(val) { | 1439 | while(val) { |
1416 | u32 v = val & 7; | 1440 | u32 v = val & 7; |
1417 | if (v != gr_activity_4_gpc0_empty_v() && | 1441 | if (v != gr_activity_4_gpc0_empty_v() && |
1418 | v != gr_activity_4_gpc0_preempted_v()) | 1442 | v != gr_activity_4_gpc0_preempted_v()) { |
1419 | return false; | 1443 | return false; |
1444 | } | ||
1420 | val >>= 3; | 1445 | val >>= 3; |
1421 | } | 1446 | } |
1422 | 1447 | ||
@@ -1480,10 +1505,11 @@ void gr_gp10b_commit_global_attrib_cb(struct gk20a *g, | |||
1480 | { | 1505 | { |
1481 | int attrBufferSize; | 1506 | int attrBufferSize; |
1482 | 1507 | ||
1483 | if (gr_ctx->preempt_ctxsw_buffer.gpu_va) | 1508 | if (gr_ctx->preempt_ctxsw_buffer.gpu_va) { |
1484 | attrBufferSize = gr_ctx->betacb_ctxsw_buffer.size; | 1509 | attrBufferSize = gr_ctx->betacb_ctxsw_buffer.size; |
1485 | else | 1510 | } else { |
1486 | attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g); | 1511 | attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g); |
1512 | } | ||
1487 | 1513 | ||
1488 | attrBufferSize /= gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(); | 1514 | attrBufferSize /= gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(); |
1489 | 1515 | ||
@@ -1544,8 +1570,9 @@ int gr_gp10b_load_smid_config(struct gk20a *g) | |||
1544 | u32 max_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS); | 1570 | u32 max_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS); |
1545 | 1571 | ||
1546 | tpc_sm_id = nvgpu_kcalloc(g, gr_cwd_sm_id__size_1_v(), sizeof(u32)); | 1572 | tpc_sm_id = nvgpu_kcalloc(g, gr_cwd_sm_id__size_1_v(), sizeof(u32)); |
1547 | if (!tpc_sm_id) | 1573 | if (!tpc_sm_id) { |
1548 | return -ENOMEM; | 1574 | return -ENOMEM; |
1575 | } | ||
1549 | 1576 | ||
1550 | /* Each NV_PGRAPH_PRI_CWD_GPC_TPC_ID can store 4 TPCs.*/ | 1577 | /* Each NV_PGRAPH_PRI_CWD_GPC_TPC_ID can store 4 TPCs.*/ |
1551 | for (i = 0; i <= ((g->gr.tpc_count-1) / 4); i++) { | 1578 | for (i = 0; i <= ((g->gr.tpc_count-1) / 4); i++) { |
@@ -1557,8 +1584,9 @@ int gr_gp10b_load_smid_config(struct gk20a *g) | |||
1557 | u32 sm_id = (i * 4) + j; | 1584 | u32 sm_id = (i * 4) + j; |
1558 | u32 bits; | 1585 | u32 bits; |
1559 | 1586 | ||
1560 | if (sm_id >= g->gr.tpc_count) | 1587 | if (sm_id >= g->gr.tpc_count) { |
1561 | break; | 1588 | break; |
1589 | } | ||
1562 | 1590 | ||
1563 | gpc_index = g->gr.sm_to_cluster[sm_id].gpc_index; | 1591 | gpc_index = g->gr.sm_to_cluster[sm_id].gpc_index; |
1564 | tpc_index = g->gr.sm_to_cluster[sm_id].tpc_index; | 1592 | tpc_index = g->gr.sm_to_cluster[sm_id].tpc_index; |
@@ -1612,12 +1640,13 @@ void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | |||
1612 | nvgpu_tegra_fuse_write_bypass(g, 0x1); | 1640 | nvgpu_tegra_fuse_write_bypass(g, 0x1); |
1613 | nvgpu_tegra_fuse_write_access_sw(g, 0x0); | 1641 | nvgpu_tegra_fuse_write_access_sw(g, 0x0); |
1614 | 1642 | ||
1615 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) | 1643 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) { |
1616 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x2); | 1644 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x2); |
1617 | else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) | 1645 | } else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) { |
1618 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x1); | 1646 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x1); |
1619 | else | 1647 | } else { |
1620 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x0); | 1648 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x0); |
1649 | } | ||
1621 | } | 1650 | } |
1622 | 1651 | ||
1623 | void gr_gp10b_get_access_map(struct gk20a *g, | 1652 | void gr_gp10b_get_access_map(struct gk20a *g, |
@@ -1709,8 +1738,9 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, | |||
1709 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, " "); | 1738 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, " "); |
1710 | 1739 | ||
1711 | tsg = tsg_gk20a_from_ch(fault_ch); | 1740 | tsg = tsg_gk20a_from_ch(fault_ch); |
1712 | if (!tsg) | 1741 | if (!tsg) { |
1713 | return -EINVAL; | 1742 | return -EINVAL; |
1743 | } | ||
1714 | 1744 | ||
1715 | gr_ctx = &tsg->gr_ctx; | 1745 | gr_ctx = &tsg->gr_ctx; |
1716 | 1746 | ||
@@ -1789,8 +1819,9 @@ static int gr_gp10b_clear_cilp_preempt_pending(struct gk20a *g, | |||
1789 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, " "); | 1819 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, " "); |
1790 | 1820 | ||
1791 | tsg = tsg_gk20a_from_ch(fault_ch); | 1821 | tsg = tsg_gk20a_from_ch(fault_ch); |
1792 | if (!tsg) | 1822 | if (!tsg) { |
1793 | return -EINVAL; | 1823 | return -EINVAL; |
1824 | } | ||
1794 | 1825 | ||
1795 | gr_ctx = &tsg->gr_ctx; | 1826 | gr_ctx = &tsg->gr_ctx; |
1796 | 1827 | ||
@@ -1831,8 +1862,9 @@ int gr_gp10b_pre_process_sm_exception(struct gk20a *g, | |||
1831 | 1862 | ||
1832 | if (fault_ch) { | 1863 | if (fault_ch) { |
1833 | tsg = tsg_gk20a_from_ch(fault_ch); | 1864 | tsg = tsg_gk20a_from_ch(fault_ch); |
1834 | if (!tsg) | 1865 | if (!tsg) { |
1835 | return -EINVAL; | 1866 | return -EINVAL; |
1867 | } | ||
1836 | 1868 | ||
1837 | cilp_enabled = (tsg->gr_ctx.compute_preempt_mode == | 1869 | cilp_enabled = (tsg->gr_ctx.compute_preempt_mode == |
1838 | NVGPU_PREEMPTION_MODE_COMPUTE_CILP); | 1870 | NVGPU_PREEMPTION_MODE_COMPUTE_CILP); |
@@ -1842,13 +1874,15 @@ int gr_gp10b_pre_process_sm_exception(struct gk20a *g, | |||
1842 | gpc, tpc, global_esr); | 1874 | gpc, tpc, global_esr); |
1843 | 1875 | ||
1844 | if (cilp_enabled && sm_debugger_attached) { | 1876 | if (cilp_enabled && sm_debugger_attached) { |
1845 | if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()) | 1877 | if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()) { |
1846 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, | 1878 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, |
1847 | gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()); | 1879 | gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()); |
1880 | } | ||
1848 | 1881 | ||
1849 | if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f()) | 1882 | if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f()) { |
1850 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, | 1883 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, |
1851 | gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f()); | 1884 | gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f()); |
1885 | } | ||
1852 | 1886 | ||
1853 | global_mask = gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f() | | 1887 | global_mask = gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f() | |
1854 | gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f() | | 1888 | gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f() | |
@@ -1930,12 +1964,14 @@ static int gr_gp10b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid) | |||
1930 | chid = g->gr.cilp_preempt_pending_chid; | 1964 | chid = g->gr.cilp_preempt_pending_chid; |
1931 | 1965 | ||
1932 | ch = gk20a_channel_get(gk20a_fifo_channel_from_chid(g, chid)); | 1966 | ch = gk20a_channel_get(gk20a_fifo_channel_from_chid(g, chid)); |
1933 | if (!ch) | 1967 | if (!ch) { |
1934 | return ret; | 1968 | return ret; |
1969 | } | ||
1935 | 1970 | ||
1936 | tsg = tsg_gk20a_from_ch(ch); | 1971 | tsg = tsg_gk20a_from_ch(ch); |
1937 | if (!tsg) | 1972 | if (!tsg) { |
1938 | return -EINVAL; | 1973 | return -EINVAL; |
1974 | } | ||
1939 | 1975 | ||
1940 | gr_ctx = &tsg->gr_ctx; | 1976 | gr_ctx = &tsg->gr_ctx; |
1941 | 1977 | ||
@@ -1974,13 +2010,15 @@ int gr_gp10b_handle_fecs_error(struct gk20a *g, | |||
1974 | gr_fecs_host_int_clear_ctxsw_intr1_clear_f()); | 2010 | gr_fecs_host_int_clear_ctxsw_intr1_clear_f()); |
1975 | 2011 | ||
1976 | ret = gr_gp10b_get_cilp_preempt_pending_chid(g, &chid); | 2012 | ret = gr_gp10b_get_cilp_preempt_pending_chid(g, &chid); |
1977 | if (ret) | 2013 | if (ret) { |
1978 | goto clean_up; | 2014 | goto clean_up; |
2015 | } | ||
1979 | 2016 | ||
1980 | ch = gk20a_channel_get( | 2017 | ch = gk20a_channel_get( |
1981 | gk20a_fifo_channel_from_chid(g, chid)); | 2018 | gk20a_fifo_channel_from_chid(g, chid)); |
1982 | if (!ch) | 2019 | if (!ch) { |
1983 | goto clean_up; | 2020 | goto clean_up; |
2021 | } | ||
1984 | 2022 | ||
1985 | 2023 | ||
1986 | /* set preempt_pending to false */ | 2024 | /* set preempt_pending to false */ |
@@ -2014,10 +2052,11 @@ u32 gp10b_gr_get_sm_hww_warp_esr(struct gk20a *g, | |||
2014 | u32 hww_warp_esr = gk20a_readl(g, | 2052 | u32 hww_warp_esr = gk20a_readl(g, |
2015 | gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset); | 2053 | gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset); |
2016 | 2054 | ||
2017 | if (!(hww_warp_esr & gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m())) | 2055 | if (!(hww_warp_esr & gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m())) { |
2018 | hww_warp_esr = set_field(hww_warp_esr, | 2056 | hww_warp_esr = set_field(hww_warp_esr, |
2019 | gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(), | 2057 | gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(), |
2020 | gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f()); | 2058 | gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f()); |
2059 | } | ||
2021 | 2060 | ||
2022 | return hww_warp_esr; | 2061 | return hww_warp_esr; |
2023 | } | 2062 | } |
@@ -2046,8 +2085,9 @@ bool gr_gp10b_suspend_context(struct channel_gk20a *ch, | |||
2046 | int err = 0; | 2085 | int err = 0; |
2047 | 2086 | ||
2048 | tsg = tsg_gk20a_from_ch(ch); | 2087 | tsg = tsg_gk20a_from_ch(ch); |
2049 | if (!tsg) | 2088 | if (!tsg) { |
2050 | return -EINVAL; | 2089 | return -EINVAL; |
2090 | } | ||
2051 | 2091 | ||
2052 | gr_ctx = &tsg->gr_ctx; | 2092 | gr_ctx = &tsg->gr_ctx; |
2053 | 2093 | ||
@@ -2058,10 +2098,11 @@ bool gr_gp10b_suspend_context(struct channel_gk20a *ch, | |||
2058 | 2098 | ||
2059 | if (gr_ctx->compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CILP) { | 2099 | if (gr_ctx->compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CILP) { |
2060 | err = gr_gp10b_set_cilp_preempt_pending(g, ch); | 2100 | err = gr_gp10b_set_cilp_preempt_pending(g, ch); |
2061 | if (err) | 2101 | if (err) { |
2062 | nvgpu_err(g, "unable to set CILP preempt pending"); | 2102 | nvgpu_err(g, "unable to set CILP preempt pending"); |
2063 | else | 2103 | } else { |
2064 | *cilp_preempt_pending = true; | 2104 | *cilp_preempt_pending = true; |
2105 | } | ||
2065 | 2106 | ||
2066 | g->ops.gr.resume_all_sms(g); | 2107 | g->ops.gr.resume_all_sms(g); |
2067 | } | 2108 | } |
@@ -2104,10 +2145,12 @@ int gr_gp10b_suspend_contexts(struct gk20a *g, | |||
2104 | 2145 | ||
2105 | ctx_resident = gr_gp10b_suspend_context(ch, | 2146 | ctx_resident = gr_gp10b_suspend_context(ch, |
2106 | &cilp_preempt_pending); | 2147 | &cilp_preempt_pending); |
2107 | if (ctx_resident) | 2148 | if (ctx_resident) { |
2108 | local_ctx_resident_ch_fd = ch_data->channel_fd; | 2149 | local_ctx_resident_ch_fd = ch_data->channel_fd; |
2109 | if (cilp_preempt_pending) | 2150 | } |
2151 | if (cilp_preempt_pending) { | ||
2110 | cilp_preempt_pending_ch = ch; | 2152 | cilp_preempt_pending_ch = ch; |
2153 | } | ||
2111 | } | 2154 | } |
2112 | 2155 | ||
2113 | nvgpu_mutex_release(&dbg_s->ch_list_lock); | 2156 | nvgpu_mutex_release(&dbg_s->ch_list_lock); |
@@ -2140,16 +2183,18 @@ int gr_gp10b_suspend_contexts(struct gk20a *g, | |||
2140 | nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), | 2183 | nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), |
2141 | NVGPU_TIMER_CPU_TIMER); | 2184 | NVGPU_TIMER_CPU_TIMER); |
2142 | do { | 2185 | do { |
2143 | if (!gr_ctx->cilp_preempt_pending) | 2186 | if (!gr_ctx->cilp_preempt_pending) { |
2144 | break; | 2187 | break; |
2188 | } | ||
2145 | 2189 | ||
2146 | nvgpu_usleep_range(delay, delay * 2); | 2190 | nvgpu_usleep_range(delay, delay * 2); |
2147 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); | 2191 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); |
2148 | } while (!nvgpu_timeout_expired(&timeout)); | 2192 | } while (!nvgpu_timeout_expired(&timeout)); |
2149 | 2193 | ||
2150 | /* If cilp is still pending at this point, timeout */ | 2194 | /* If cilp is still pending at this point, timeout */ |
2151 | if (gr_ctx->cilp_preempt_pending) | 2195 | if (gr_ctx->cilp_preempt_pending) { |
2152 | err = -ETIMEDOUT; | 2196 | err = -ETIMEDOUT; |
2197 | } | ||
2153 | } | 2198 | } |
2154 | 2199 | ||
2155 | *ctx_resident_ch_fd = local_ctx_resident_ch_fd; | 2200 | *ctx_resident_ch_fd = local_ctx_resident_ch_fd; |
@@ -2168,25 +2213,29 @@ int gr_gp10b_set_boosted_ctx(struct channel_gk20a *ch, | |||
2168 | int err = 0; | 2213 | int err = 0; |
2169 | 2214 | ||
2170 | tsg = tsg_gk20a_from_ch(ch); | 2215 | tsg = tsg_gk20a_from_ch(ch); |
2171 | if (!tsg) | 2216 | if (!tsg) { |
2172 | return -EINVAL; | 2217 | return -EINVAL; |
2218 | } | ||
2173 | 2219 | ||
2174 | gr_ctx = &tsg->gr_ctx; | 2220 | gr_ctx = &tsg->gr_ctx; |
2175 | gr_ctx->boosted_ctx = boost; | 2221 | gr_ctx->boosted_ctx = boost; |
2176 | mem = &gr_ctx->mem; | 2222 | mem = &gr_ctx->mem; |
2177 | 2223 | ||
2178 | err = gk20a_disable_channel_tsg(g, ch); | 2224 | err = gk20a_disable_channel_tsg(g, ch); |
2179 | if (err) | 2225 | if (err) { |
2180 | return err; | 2226 | return err; |
2227 | } | ||
2181 | 2228 | ||
2182 | err = gk20a_fifo_preempt(g, ch); | 2229 | err = gk20a_fifo_preempt(g, ch); |
2183 | if (err) | 2230 | if (err) { |
2184 | goto enable_ch; | 2231 | goto enable_ch; |
2232 | } | ||
2185 | 2233 | ||
2186 | if (g->ops.gr.update_boosted_ctx) | 2234 | if (g->ops.gr.update_boosted_ctx) { |
2187 | g->ops.gr.update_boosted_ctx(g, mem, gr_ctx); | 2235 | g->ops.gr.update_boosted_ctx(g, mem, gr_ctx); |
2188 | else | 2236 | } else { |
2189 | err = -ENOSYS; | 2237 | err = -ENOSYS; |
2238 | } | ||
2190 | 2239 | ||
2191 | enable_ch: | 2240 | enable_ch: |
2192 | gk20a_enable_channel_tsg(g, ch); | 2241 | gk20a_enable_channel_tsg(g, ch); |
@@ -2216,12 +2265,14 @@ int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, | |||
2216 | int err = 0; | 2265 | int err = 0; |
2217 | 2266 | ||
2218 | class = ch->obj_class; | 2267 | class = ch->obj_class; |
2219 | if (!class) | 2268 | if (!class) { |
2220 | return -EINVAL; | 2269 | return -EINVAL; |
2270 | } | ||
2221 | 2271 | ||
2222 | tsg = tsg_gk20a_from_ch(ch); | 2272 | tsg = tsg_gk20a_from_ch(ch); |
2223 | if (!tsg) | 2273 | if (!tsg) { |
2224 | return -EINVAL; | 2274 | return -EINVAL; |
2275 | } | ||
2225 | 2276 | ||
2226 | vm = tsg->vm; | 2277 | vm = tsg->vm; |
2227 | gr_ctx = &tsg->gr_ctx; | 2278 | gr_ctx = &tsg->gr_ctx; |
@@ -2229,15 +2280,18 @@ int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, | |||
2229 | 2280 | ||
2230 | /* skip setting anything if both modes are already set */ | 2281 | /* skip setting anything if both modes are already set */ |
2231 | if (graphics_preempt_mode && | 2282 | if (graphics_preempt_mode && |
2232 | (graphics_preempt_mode == gr_ctx->graphics_preempt_mode)) | 2283 | (graphics_preempt_mode == gr_ctx->graphics_preempt_mode)) { |
2233 | graphics_preempt_mode = 0; | 2284 | graphics_preempt_mode = 0; |
2285 | } | ||
2234 | 2286 | ||
2235 | if (compute_preempt_mode && | 2287 | if (compute_preempt_mode && |
2236 | (compute_preempt_mode == gr_ctx->compute_preempt_mode)) | 2288 | (compute_preempt_mode == gr_ctx->compute_preempt_mode)) { |
2237 | compute_preempt_mode = 0; | 2289 | compute_preempt_mode = 0; |
2290 | } | ||
2238 | 2291 | ||
2239 | if (graphics_preempt_mode == 0 && compute_preempt_mode == 0) | 2292 | if (graphics_preempt_mode == 0 && compute_preempt_mode == 0) { |
2240 | return 0; | 2293 | return 0; |
2294 | } | ||
2241 | 2295 | ||
2242 | if (g->ops.gr.set_ctxsw_preemption_mode) { | 2296 | if (g->ops.gr.set_ctxsw_preemption_mode) { |
2243 | 2297 | ||
@@ -2257,12 +2311,14 @@ int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, | |||
2257 | } | 2311 | } |
2258 | 2312 | ||
2259 | err = gk20a_disable_channel_tsg(g, ch); | 2313 | err = gk20a_disable_channel_tsg(g, ch); |
2260 | if (err) | 2314 | if (err) { |
2261 | return err; | 2315 | return err; |
2316 | } | ||
2262 | 2317 | ||
2263 | err = gk20a_fifo_preempt(g, ch); | 2318 | err = gk20a_fifo_preempt(g, ch); |
2264 | if (err) | 2319 | if (err) { |
2265 | goto enable_ch; | 2320 | goto enable_ch; |
2321 | } | ||
2266 | 2322 | ||
2267 | if (g->ops.gr.update_ctxsw_preemption_mode) { | 2323 | if (g->ops.gr.update_ctxsw_preemption_mode) { |
2268 | g->ops.gr.update_ctxsw_preemption_mode(ch->g, | 2324 | g->ops.gr.update_ctxsw_preemption_mode(ch->g, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index efd66b5d..e66fcff6 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -762,8 +762,9 @@ int gp10b_init_hal(struct gk20a *g) | |||
762 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false); | 762 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false); |
763 | 763 | ||
764 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ | 764 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ |
765 | if (gops->fuse.check_priv_security(g)) | 765 | if (gops->fuse.check_priv_security(g)) { |
766 | return -EINVAL; /* Do not boot gpu */ | 766 | return -EINVAL; /* Do not boot gpu */ |
767 | } | ||
767 | 768 | ||
768 | /* priv security dependent ops */ | 769 | /* priv security dependent ops */ |
769 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | 770 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 063bda7c..9851fc5d 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c | |||
@@ -143,8 +143,9 @@ void mc_gp10b_isr_stall(struct gk20a *g) | |||
143 | g->ops.mc.is_intr_nvlink_pending(g, mc_intr_0)) { | 143 | g->ops.mc.is_intr_nvlink_pending(g, mc_intr_0)) { |
144 | g->ops.nvlink.isr(g); | 144 | g->ops.nvlink.isr(g); |
145 | } | 145 | } |
146 | if (mc_intr_0 & mc_intr_pfb_pending_f() && g->ops.fb.fbpa_isr) | 146 | if (mc_intr_0 & mc_intr_pfb_pending_f() && g->ops.fb.fbpa_isr) { |
147 | g->ops.fb.fbpa_isr(g); | 147 | g->ops.fb.fbpa_isr(g); |
148 | } | ||
148 | 149 | ||
149 | nvgpu_log(g, gpu_dbg_intr, "stall intr done 0x%08x\n", mc_intr_0); | 150 | nvgpu_log(g, gpu_dbg_intr, "stall intr done 0x%08x\n", mc_intr_0); |
150 | 151 | ||
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 5a24adc0..342dc486 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c | |||
@@ -59,13 +59,15 @@ int gp10b_init_bar2_vm(struct gk20a *g) | |||
59 | mm->bar2.vm = nvgpu_vm_init(g, big_page_size, SZ_4K, | 59 | mm->bar2.vm = nvgpu_vm_init(g, big_page_size, SZ_4K, |
60 | mm->bar2.aperture_size - SZ_4K, | 60 | mm->bar2.aperture_size - SZ_4K, |
61 | mm->bar2.aperture_size, false, false, "bar2"); | 61 | mm->bar2.aperture_size, false, false, "bar2"); |
62 | if (!mm->bar2.vm) | 62 | if (!mm->bar2.vm) { |
63 | return -ENOMEM; | 63 | return -ENOMEM; |
64 | } | ||
64 | 65 | ||
65 | /* allocate instance mem for bar2 */ | 66 | /* allocate instance mem for bar2 */ |
66 | err = g->ops.mm.alloc_inst_block(g, inst_block); | 67 | err = g->ops.mm.alloc_inst_block(g, inst_block); |
67 | if (err) | 68 | if (err) { |
68 | goto clean_up_va; | 69 | goto clean_up_va; |
70 | } | ||
69 | 71 | ||
70 | g->ops.mm.init_inst_block(inst_block, mm->bar2.vm, big_page_size); | 72 | g->ops.mm.init_inst_block(inst_block, mm->bar2.vm, big_page_size); |
71 | 73 | ||
@@ -129,11 +131,13 @@ static void update_gmmu_pde0_locked(struct vm_gk20a *vm, | |||
129 | small_valid = attrs->pgsz == GMMU_PAGE_SIZE_SMALL; | 131 | small_valid = attrs->pgsz == GMMU_PAGE_SIZE_SMALL; |
130 | big_valid = attrs->pgsz == GMMU_PAGE_SIZE_BIG; | 132 | big_valid = attrs->pgsz == GMMU_PAGE_SIZE_BIG; |
131 | 133 | ||
132 | if (small_valid) | 134 | if (small_valid) { |
133 | small_addr = phys_addr >> gmmu_new_dual_pde_address_shift_v(); | 135 | small_addr = phys_addr >> gmmu_new_dual_pde_address_shift_v(); |
136 | } | ||
134 | 137 | ||
135 | if (big_valid) | 138 | if (big_valid) { |
136 | big_addr = phys_addr >> gmmu_new_dual_pde_address_big_shift_v(); | 139 | big_addr = phys_addr >> gmmu_new_dual_pde_address_big_shift_v(); |
140 | } | ||
137 | 141 | ||
138 | if (small_valid) { | 142 | if (small_valid) { |
139 | pde_v[2] |= | 143 | pde_v[2] |= |
@@ -195,24 +199,28 @@ static void __update_pte(struct vm_gk20a *vm, | |||
195 | 199 | ||
196 | pte_w[0] = pte_valid | pte_addr | pte_tgt; | 200 | pte_w[0] = pte_valid | pte_addr | pte_tgt; |
197 | 201 | ||
198 | if (attrs->priv) | 202 | if (attrs->priv) { |
199 | pte_w[0] |= gmmu_new_pte_privilege_true_f(); | 203 | pte_w[0] |= gmmu_new_pte_privilege_true_f(); |
204 | } | ||
200 | 205 | ||
201 | pte_w[1] = phys_addr >> (24 + gmmu_new_pte_address_shift_v()) | | 206 | pte_w[1] = phys_addr >> (24 + gmmu_new_pte_address_shift_v()) | |
202 | gmmu_new_pte_kind_f(attrs->kind_v) | | 207 | gmmu_new_pte_kind_f(attrs->kind_v) | |
203 | gmmu_new_pte_comptagline_f((u32)(attrs->ctag / | 208 | gmmu_new_pte_comptagline_f((u32)(attrs->ctag / |
204 | ctag_granularity)); | 209 | ctag_granularity)); |
205 | 210 | ||
206 | if (attrs->rw_flag == gk20a_mem_flag_read_only) | 211 | if (attrs->rw_flag == gk20a_mem_flag_read_only) { |
207 | pte_w[0] |= gmmu_new_pte_read_only_true_f(); | 212 | pte_w[0] |= gmmu_new_pte_read_only_true_f(); |
213 | } | ||
208 | 214 | ||
209 | if (!attrs->valid && !attrs->cacheable) | 215 | if (!attrs->valid && !attrs->cacheable) { |
210 | pte_w[0] |= gmmu_new_pte_read_only_true_f(); | 216 | pte_w[0] |= gmmu_new_pte_read_only_true_f(); |
211 | else if (!attrs->cacheable) | 217 | } else if (!attrs->cacheable) { |
212 | pte_w[0] |= gmmu_new_pte_vol_true_f(); | 218 | pte_w[0] |= gmmu_new_pte_vol_true_f(); |
219 | } | ||
213 | 220 | ||
214 | if (attrs->ctag) | 221 | if (attrs->ctag) { |
215 | attrs->ctag += page_size; | 222 | attrs->ctag += page_size; |
223 | } | ||
216 | 224 | ||
217 | } | 225 | } |
218 | 226 | ||
@@ -235,10 +243,11 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm, | |||
235 | u32 pd_offset = pd_offset_from_index(l, pd_idx); | 243 | u32 pd_offset = pd_offset_from_index(l, pd_idx); |
236 | u32 pte_w[2] = {0, 0}; | 244 | u32 pte_w[2] = {0, 0}; |
237 | 245 | ||
238 | if (phys_addr) | 246 | if (phys_addr) { |
239 | __update_pte(vm, pte_w, phys_addr, attrs); | 247 | __update_pte(vm, pte_w, phys_addr, attrs); |
240 | else if (attrs->sparse) | 248 | } else if (attrs->sparse) { |
241 | __update_pte_sparse(pte_w); | 249 | __update_pte_sparse(pte_w); |
250 | } | ||
242 | 251 | ||
243 | pte_dbg(g, attrs, | 252 | pte_dbg(g, attrs, |
244 | "vm=%s " | 253 | "vm=%s " |
@@ -283,8 +292,9 @@ static u32 gp10b_get_pde0_pgsz(struct gk20a *g, const struct gk20a_mmu_level *l, | |||
283 | u32 i; | 292 | u32 i; |
284 | u32 pgsz = GMMU_NR_PAGE_SIZES; | 293 | u32 pgsz = GMMU_NR_PAGE_SIZES; |
285 | 294 | ||
286 | if (!pd->mem) | 295 | if (!pd->mem) { |
287 | return pgsz; | 296 | return pgsz; |
297 | } | ||
288 | 298 | ||
289 | for (i = 0; i < GP10B_PDE0_ENTRY_SIZE >> 2; i++) { | 299 | for (i = 0; i < GP10B_PDE0_ENTRY_SIZE >> 2; i++) { |
290 | pde_v[i] = nvgpu_mem_rd32(g, pd->mem, pde_offset + i); | 300 | pde_v[i] = nvgpu_mem_rd32(g, pd->mem, pde_offset + i); |
@@ -300,8 +310,9 @@ static u32 gp10b_get_pde0_pgsz(struct gk20a *g, const struct gk20a_mmu_level *l, | |||
300 | gmmu_new_dual_pde_address_small_sys_f(~0))) << | 310 | gmmu_new_dual_pde_address_small_sys_f(~0))) << |
301 | gmmu_new_dual_pde_address_shift_v(); | 311 | gmmu_new_dual_pde_address_shift_v(); |
302 | 312 | ||
303 | if (addr) | 313 | if (addr) { |
304 | pgsz = GMMU_PAGE_SIZE_SMALL; | 314 | pgsz = GMMU_PAGE_SIZE_SMALL; |
315 | } | ||
305 | } | 316 | } |
306 | 317 | ||
307 | if (pde_v[0] & (gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() | | 318 | if (pde_v[0] & (gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() | |
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index d6497173..32e7297f 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -179,11 +179,13 @@ int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) | |||
179 | u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; | 179 | u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; |
180 | 180 | ||
181 | /* GM20B PMU supports loading FECS and GPCCS only */ | 181 | /* GM20B PMU supports loading FECS and GPCCS only */ |
182 | if (falconidmask == 0) | 182 | if (falconidmask == 0) { |
183 | return -EINVAL; | 183 | return -EINVAL; |
184 | } | ||
184 | if (falconidmask & ~((1 << LSF_FALCON_ID_FECS) | | 185 | if (falconidmask & ~((1 << LSF_FALCON_ID_FECS) | |
185 | (1 << LSF_FALCON_ID_GPCCS))) | 186 | (1 << LSF_FALCON_ID_GPCCS))) { |
186 | return -EINVAL; | 187 | return -EINVAL; |
188 | } | ||
187 | g->pmu_lsf_loaded_falcon_id = 0; | 189 | g->pmu_lsf_loaded_falcon_id = 0; |
188 | /* check whether pmu is ready to bootstrap lsf if not wait for it */ | 190 | /* check whether pmu is ready to bootstrap lsf if not wait for it */ |
189 | if (!g->pmu_lsf_pmu_wpr_init_done) { | 191 | if (!g->pmu_lsf_pmu_wpr_init_done) { |
@@ -201,8 +203,9 @@ int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) | |||
201 | pmu_wait_message_cond(&g->pmu, | 203 | pmu_wait_message_cond(&g->pmu, |
202 | gk20a_get_gr_idle_timeout(g), | 204 | gk20a_get_gr_idle_timeout(g), |
203 | &g->pmu_lsf_loaded_falcon_id, falconidmask); | 205 | &g->pmu_lsf_loaded_falcon_id, falconidmask); |
204 | if (g->pmu_lsf_loaded_falcon_id != falconidmask) | 206 | if (g->pmu_lsf_loaded_falcon_id != falconidmask) { |
205 | return -ETIMEDOUT; | 207 | return -ETIMEDOUT; |
208 | } | ||
206 | return 0; | 209 | return 0; |
207 | } | 210 | } |
208 | 211 | ||
@@ -247,8 +250,9 @@ int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) | |||
247 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 250 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
248 | pmu_handle_gr_param_msg, pmu, &seq, ~0); | 251 | pmu_handle_gr_param_msg, pmu, &seq, ~0); |
249 | 252 | ||
250 | } else | 253 | } else { |
251 | return -EINVAL; | 254 | return -EINVAL; |
255 | } | ||
252 | 256 | ||
253 | return 0; | 257 | return 0; |
254 | } | 258 | } |
@@ -330,8 +334,9 @@ int gp10b_init_pmu_setup_hw1(struct gk20a *g) | |||
330 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); | 334 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); |
331 | 335 | ||
332 | err = g->ops.pmu.pmu_nsbootstrap(pmu); | 336 | err = g->ops.pmu.pmu_nsbootstrap(pmu); |
333 | if (err) | 337 | if (err) { |
334 | return err; | 338 | return err; |
339 | } | ||
335 | 340 | ||
336 | nvgpu_log_fn(g, "done"); | 341 | nvgpu_log_fn(g, "done"); |
337 | return 0; | 342 | return 0; |