diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c | 36 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 18 |
2 files changed, 53 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c b/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c index d42afb4c..ee14d00c 100644 --- a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c +++ b/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B specific sysfs files | 2 | * GP10B specific sysfs files |
3 | * | 3 | * |
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -18,6 +18,8 @@ | |||
18 | #include "gk20a/gk20a.h" | 18 | #include "gk20a/gk20a.h" |
19 | #include "gp10b_sysfs.h" | 19 | #include "gp10b_sysfs.h" |
20 | 20 | ||
21 | #include <nvgpu/hw/gp10b/hw_gr_gp10b.h> | ||
22 | |||
21 | #define ROOTRW (S_IRWXU|S_IRGRP|S_IROTH) | 23 | #define ROOTRW (S_IRWXU|S_IRGRP|S_IROTH) |
22 | 24 | ||
23 | static ssize_t ecc_enable_store(struct device *dev, | 25 | static ssize_t ecc_enable_store(struct device *dev, |
@@ -49,12 +51,43 @@ static ssize_t ecc_enable_read(struct device *dev, | |||
49 | 51 | ||
50 | static DEVICE_ATTR(ecc_enable, ROOTRW, ecc_enable_read, ecc_enable_store); | 52 | static DEVICE_ATTR(ecc_enable, ROOTRW, ecc_enable_read, ecc_enable_store); |
51 | 53 | ||
54 | |||
55 | static ssize_t czf_bypass_store(struct device *dev, | ||
56 | struct device_attribute *attr, const char *buf, size_t count) | ||
57 | { | ||
58 | struct gk20a *g = get_gk20a(dev); | ||
59 | unsigned long val; | ||
60 | |||
61 | if (kstrtoul(buf, 10, &val) < 0) | ||
62 | return -EINVAL; | ||
63 | |||
64 | if (val >= 4) | ||
65 | return -EINVAL; | ||
66 | |||
67 | g->gr.czf_bypass = val; | ||
68 | |||
69 | return count; | ||
70 | } | ||
71 | |||
72 | static ssize_t czf_bypass_read(struct device *dev, | ||
73 | struct device_attribute *attr, char *buf) | ||
74 | { | ||
75 | struct gk20a *g = get_gk20a(dev); | ||
76 | |||
77 | return sprintf(buf, "%d\n", g->gr.czf_bypass); | ||
78 | } | ||
79 | |||
80 | static DEVICE_ATTR(czf_bypass, ROOTRW, czf_bypass_read, czf_bypass_store); | ||
81 | |||
52 | void gp10b_create_sysfs(struct device *dev) | 82 | void gp10b_create_sysfs(struct device *dev) |
53 | { | 83 | { |
54 | struct gk20a *g = get_gk20a(dev); | 84 | struct gk20a *g = get_gk20a(dev); |
55 | int error = 0; | 85 | int error = 0; |
56 | 86 | ||
87 | g->gr.czf_bypass = gr_gpc0_prop_debug1_czf_bypass_init_v(); | ||
88 | |||
57 | error |= device_create_file(dev, &dev_attr_ecc_enable); | 89 | error |= device_create_file(dev, &dev_attr_ecc_enable); |
90 | error |= device_create_file(dev, &dev_attr_czf_bypass); | ||
58 | if (error) | 91 | if (error) |
59 | nvgpu_err(g, "Failed to create sysfs attributes!\n"); | 92 | nvgpu_err(g, "Failed to create sysfs attributes!\n"); |
60 | } | 93 | } |
@@ -62,4 +95,5 @@ void gp10b_create_sysfs(struct device *dev) | |||
62 | void gp10b_remove_sysfs(struct device *dev) | 95 | void gp10b_remove_sysfs(struct device *dev) |
63 | { | 96 | { |
64 | device_remove_file(dev, &dev_attr_ecc_enable); | 97 | device_remove_file(dev, &dev_attr_ecc_enable); |
98 | device_remove_file(dev, &dev_attr_czf_bypass); | ||
65 | } | 99 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index a43252de..1853aaec 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #include "gk20a/gk20a.h" | 27 | #include "gk20a/gk20a.h" |
28 | #include "gk20a/gr_gk20a.h" | 28 | #include "gk20a/gr_gk20a.h" |
29 | #include "gk20a/dbg_gpu_gk20a.h" | 29 | #include "gk20a/dbg_gpu_gk20a.h" |
30 | #include "gk20a/regops_gk20a.h" | ||
30 | 31 | ||
31 | #include "gm20b/gr_gm20b.h" | 32 | #include "gm20b/gr_gm20b.h" |
32 | #include "gp10b/gr_gp10b.h" | 33 | #include "gp10b/gr_gp10b.h" |
@@ -2304,6 +2305,22 @@ static void gr_gp10b_write_preemption_ptr(struct gk20a *g, | |||
2304 | 2305 | ||
2305 | } | 2306 | } |
2306 | 2307 | ||
2308 | int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch) | ||
2309 | { | ||
2310 | struct nvgpu_dbg_gpu_reg_op ops; | ||
2311 | |||
2312 | ops.op = REGOP(WRITE_32); | ||
2313 | ops.type = REGOP(TYPE_GR_CTX); | ||
2314 | ops.status = REGOP(STATUS_SUCCESS); | ||
2315 | ops.value_hi = 0; | ||
2316 | ops.and_n_mask_lo = gr_gpc0_prop_debug1_czf_bypass_m(); | ||
2317 | ops.and_n_mask_hi = 0; | ||
2318 | ops.offset = gr_gpc0_prop_debug1_r(); | ||
2319 | ops.value_lo = gr_gpc0_prop_debug1_czf_bypass_f( | ||
2320 | g->gr.czf_bypass); | ||
2321 | |||
2322 | return __gr_gk20a_exec_ctx_ops(ch, &ops, 1, 1, 0, false); | ||
2323 | } | ||
2307 | 2324 | ||
2308 | void gp10b_init_gr(struct gpu_ops *gops) | 2325 | void gp10b_init_gr(struct gpu_ops *gops) |
2309 | { | 2326 | { |
@@ -2355,4 +2372,5 @@ void gp10b_init_gr(struct gpu_ops *gops) | |||
2355 | gops->gr.load_smid_config = gr_gp10b_load_smid_config; | 2372 | gops->gr.load_smid_config = gr_gp10b_load_smid_config; |
2356 | gops->gr.set_boosted_ctx = gr_gp10b_set_boosted_ctx; | 2373 | gops->gr.set_boosted_ctx = gr_gp10b_set_boosted_ctx; |
2357 | gops->gr.update_boosted_ctx = gr_gp10b_update_boosted_ctx; | 2374 | gops->gr.update_boosted_ctx = gr_gp10b_update_boosted_ctx; |
2375 | gops->gr.set_czf_bypass = gr_gp10b_set_czf_bypass; | ||
2358 | } | 2376 | } |