diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 9 |
2 files changed, 9 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index d2b86e51..05fbeb21 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -1600,15 +1600,15 @@ static void gr_gp10b_init_cyclestats(struct gk20a *g) | |||
1600 | 1600 | ||
1601 | static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 1601 | static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
1602 | { | 1602 | { |
1603 | nvgpu_tegra_fuse_write_bypass(0x1); | 1603 | nvgpu_tegra_fuse_write_bypass(g, 0x1); |
1604 | nvgpu_tegra_fuse_write_access_sw(0x0); | 1604 | nvgpu_tegra_fuse_write_access_sw(g, 0x0); |
1605 | 1605 | ||
1606 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) | 1606 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) |
1607 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x2); | 1607 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x2); |
1608 | else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) | 1608 | else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) |
1609 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x1); | 1609 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x1); |
1610 | else | 1610 | else |
1611 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0); | 1611 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x0); |
1612 | } | 1612 | } |
1613 | 1613 | ||
1614 | static void gr_gp10b_get_access_map(struct gk20a *g, | 1614 | static void gr_gp10b_get_access_map(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index e9a9b922..da8044cd 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -378,13 +378,12 @@ static void pmu_dump_security_fuses_gp10b(struct gk20a *g) | |||
378 | { | 378 | { |
379 | u32 val; | 379 | u32 val; |
380 | 380 | ||
381 | nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x", | 381 | nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0: 0x%x", |
382 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); | 382 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); |
383 | nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", | 383 | nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0: 0x%x", |
384 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); | 384 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); |
385 | nvgpu_tegra_fuse_read_gcplex_config_fuse(&val); | 385 | nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val); |
386 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", | 386 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val); |
387 | val); | ||
388 | } | 387 | } |
389 | 388 | ||
390 | static bool gp10b_is_pmu_supported(struct gk20a *g) | 389 | static bool gp10b_is_pmu_supported(struct gk20a *g) |