diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 17 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h | 38 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 8 |
3 files changed, 54 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index 4766e0e4..45de221e 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | |||
@@ -23,6 +23,7 @@ | |||
23 | #include "hw_ccsr_gp10b.h" | 23 | #include "hw_ccsr_gp10b.h" |
24 | #include "hw_fifo_gp10b.h" | 24 | #include "hw_fifo_gp10b.h" |
25 | #include "hw_ram_gp10b.h" | 25 | #include "hw_ram_gp10b.h" |
26 | #include "hw_top_gp10b.h" | ||
26 | 27 | ||
27 | static void gp10b_set_pdb_fault_replay_flags(struct gk20a *g, | 28 | static void gp10b_set_pdb_fault_replay_flags(struct gk20a *g, |
28 | struct mem_desc *mem) | 29 | struct mem_desc *mem) |
@@ -181,10 +182,26 @@ static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c) | |||
181 | return 0; | 182 | return 0; |
182 | } | 183 | } |
183 | 184 | ||
185 | static int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type) | ||
186 | { | ||
187 | int ret = ENGINE_INVAL_GK20A; | ||
188 | |||
189 | gk20a_dbg_info("engine type %d", engine_type); | ||
190 | if (engine_type == top_device_info_type_enum_graphics_v()) | ||
191 | ret = ENGINE_GR_GK20A; | ||
192 | else if (engine_type == top_device_info_type_enum_lce_v()) | ||
193 | ret = ENGINE_CE2_GK20A; | ||
194 | else | ||
195 | gk20a_err(g->dev, "unknown engine %d", engine_type); | ||
196 | |||
197 | return ret; | ||
198 | } | ||
199 | |||
184 | void gp10b_init_fifo(struct gpu_ops *gops) | 200 | void gp10b_init_fifo(struct gpu_ops *gops) |
185 | { | 201 | { |
186 | gm20b_init_fifo(gops); | 202 | gm20b_init_fifo(gops); |
187 | gops->fifo.setup_ramfc = channel_gp10b_setup_ramfc; | 203 | gops->fifo.setup_ramfc = channel_gp10b_setup_ramfc; |
188 | gops->fifo.get_pbdma_signature = gp10b_fifo_get_pbdma_signature; | 204 | gops->fifo.get_pbdma_signature = gp10b_fifo_get_pbdma_signature; |
189 | gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc; | 205 | gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc; |
206 | gops->fifo.engine_enum_from_type = gp10b_fifo_engine_enum_from_type; | ||
190 | } | 207 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h index ab6f6373..5376717f 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -138,13 +138,37 @@ static inline u32 top_device_info_type_enum_graphics_f(void) | |||
138 | { | 138 | { |
139 | return 0x0; | 139 | return 0x0; |
140 | } | 140 | } |
141 | static inline u32 top_device_info_type_enum_copy0_v(void) | 141 | static inline u32 top_device_info_type_enum_copy2_v(void) |
142 | { | 142 | { |
143 | return 0x00000001; | 143 | return 0x00000003; |
144 | } | ||
145 | static inline u32 top_device_info_type_enum_copy2_f(void) | ||
146 | { | ||
147 | return 0xc; | ||
148 | } | ||
149 | static inline u32 top_device_info_type_enum_lce_v(void) | ||
150 | { | ||
151 | return 0x00000013; | ||
152 | } | ||
153 | static inline u32 top_device_info_type_enum_lce_f(void) | ||
154 | { | ||
155 | return 0x4c; | ||
156 | } | ||
157 | static inline u32 top_device_info_engine_v(u32 r) | ||
158 | { | ||
159 | return (r >> 5) & 0x1; | ||
160 | } | ||
161 | static inline u32 top_device_info_runlist_v(u32 r) | ||
162 | { | ||
163 | return (r >> 4) & 0x1; | ||
164 | } | ||
165 | static inline u32 top_device_info_intr_v(u32 r) | ||
166 | { | ||
167 | return (r >> 3) & 0x1; | ||
144 | } | 168 | } |
145 | static inline u32 top_device_info_type_enum_copy0_f(void) | 169 | static inline u32 top_device_info_reset_v(u32 r) |
146 | { | 170 | { |
147 | return 0x4; | 171 | return (r >> 2) & 0x1; |
148 | } | 172 | } |
149 | static inline u32 top_device_info_entry_v(u32 r) | 173 | static inline u32 top_device_info_entry_v(u32 r) |
150 | { | 174 | { |
@@ -158,4 +182,8 @@ static inline u32 top_device_info_entry_enum_v(void) | |||
158 | { | 182 | { |
159 | return 0x00000002; | 183 | return 0x00000002; |
160 | } | 184 | } |
185 | static inline u32 top_device_info_entry_engine_type_v(void) | ||
186 | { | ||
187 | return 0x00000002; | ||
188 | } | ||
161 | #endif | 189 | #endif |
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 47c8fcc6..4d9573d1 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c | |||
@@ -108,9 +108,9 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | |||
108 | 108 | ||
109 | gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); | 109 | gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); |
110 | 110 | ||
111 | if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) | 111 | if (mc_intr_0 & g->fifo.engine_info[ENGINE_GR_GK20A].intr_mask) |
112 | gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); | 112 | gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); |
113 | if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) | 113 | if (mc_intr_0 & g->fifo.engine_info[ENGINE_CE2_GK20A].intr_mask |
114 | && g->ops.ce2.isr_stall) | 114 | && g->ops.ce2.isr_stall) |
115 | g->ops.ce2.isr_stall(g); | 115 | g->ops.ce2.isr_stall(g); |
116 | if (mc_intr_0 & mc_intr_pfifo_pending_f()) | 116 | if (mc_intr_0 & mc_intr_pfifo_pending_f()) |
@@ -142,9 +142,9 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) | |||
142 | 142 | ||
143 | if (mc_intr_1 & mc_intr_pfifo_pending_f()) | 143 | if (mc_intr_1 & mc_intr_pfifo_pending_f()) |
144 | gk20a_fifo_nonstall_isr(g); | 144 | gk20a_fifo_nonstall_isr(g); |
145 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) | 145 | if (mc_intr_1 & g->fifo.engine_info[ENGINE_GR_GK20A].intr_mask) |
146 | gk20a_gr_nonstall_isr(g); | 146 | gk20a_gr_nonstall_isr(g); |
147 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) | 147 | if (mc_intr_1 & g->fifo.engine_info[ENGINE_CE2_GK20A].intr_mask |
148 | && g->ops.ce2.isr_nonstall) | 148 | && g->ops.ce2.isr_nonstall) |
149 | g->ops.ce2.isr_nonstall(g); | 149 | g->ops.ce2.isr_nonstall(g); |
150 | 150 | ||