diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 115 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 8 |
2 files changed, 120 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index f4a63fad..b7a52be0 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -19,7 +19,8 @@ | |||
19 | 19 | ||
20 | #include "gm20b/gr_gm20b.h" /* for MAXWELL classes */ | 20 | #include "gm20b/gr_gm20b.h" /* for MAXWELL classes */ |
21 | #include "gp10b/gr_gp10b.h" | 21 | #include "gp10b/gr_gp10b.h" |
22 | 22 | #include "hw_gr_gp10b.h" | |
23 | #include "hw_proj_gp10b.h" | ||
23 | 24 | ||
24 | bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num) | 25 | bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num) |
25 | { | 26 | { |
@@ -47,8 +48,120 @@ bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num) | |||
47 | return valid; | 48 | return valid; |
48 | } | 49 | } |
49 | 50 | ||
51 | int gr_gp10b_commit_global_cb_manager(struct gk20a *g, | ||
52 | struct channel_gk20a *c, bool patch) | ||
53 | { | ||
54 | struct gr_gk20a *gr = &g->gr; | ||
55 | struct channel_ctx_gk20a *ch_ctx = NULL; | ||
56 | u32 attrib_offset_in_chunk = 0; | ||
57 | u32 alpha_offset_in_chunk = 0; | ||
58 | u32 pd_ab_max_output; | ||
59 | u32 gpc_index, ppc_index; | ||
60 | u32 temp; | ||
61 | u32 cbm_cfg_size1, cbm_cfg_size2; | ||
62 | |||
63 | gk20a_dbg_fn(""); | ||
64 | |||
65 | if (patch) { | ||
66 | int err; | ||
67 | ch_ctx = &c->ch_ctx; | ||
68 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); | ||
69 | if (err) | ||
70 | return err; | ||
71 | } | ||
72 | |||
73 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_beta_r(), | ||
74 | gr->attrib_cb_default_size, patch); | ||
75 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_alpha_r(), | ||
76 | gr->alpha_cb_default_size, patch); | ||
77 | |||
78 | pd_ab_max_output = (gr->alpha_cb_default_size * | ||
79 | gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v()) / | ||
80 | gr_pd_ab_dist_cfg1_max_output_granularity_v(); | ||
81 | |||
82 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg1_r(), | ||
83 | gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output) | | ||
84 | gr_pd_ab_dist_cfg1_max_batches_init_f(), patch); | ||
85 | |||
86 | alpha_offset_in_chunk = attrib_offset_in_chunk + | ||
87 | gr->tpc_count * gr->attrib_cb_size; | ||
88 | |||
89 | for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { | ||
90 | temp = proj_gpc_stride_v() * gpc_index; | ||
91 | for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index]; | ||
92 | ppc_index++) { | ||
93 | cbm_cfg_size1 = gr->attrib_cb_default_size * | ||
94 | gr->pes_tpc_count[ppc_index][gpc_index]; | ||
95 | cbm_cfg_size2 = gr->alpha_cb_default_size * | ||
96 | gr->pes_tpc_count[ppc_index][gpc_index]; | ||
97 | |||
98 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
99 | gr_gpc0_ppc0_cbm_beta_cb_size_r() + temp + | ||
100 | proj_ppc_in_gpc_stride_v() * ppc_index, | ||
101 | cbm_cfg_size1, patch); | ||
102 | |||
103 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
104 | gr_gpc0_ppc0_cbm_beta_cb_offset_r() + temp + | ||
105 | proj_ppc_in_gpc_stride_v() * ppc_index, | ||
106 | attrib_offset_in_chunk, patch); | ||
107 | |||
108 | attrib_offset_in_chunk += gr->attrib_cb_size * | ||
109 | gr->pes_tpc_count[ppc_index][gpc_index]; | ||
110 | |||
111 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
112 | gr_gpc0_ppc0_cbm_alpha_cb_size_r() + temp + | ||
113 | proj_ppc_in_gpc_stride_v() * ppc_index, | ||
114 | cbm_cfg_size2, patch); | ||
115 | |||
116 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
117 | gr_gpc0_ppc0_cbm_alpha_cb_offset_r() + temp + | ||
118 | proj_ppc_in_gpc_stride_v() * ppc_index, | ||
119 | alpha_offset_in_chunk, patch); | ||
120 | |||
121 | alpha_offset_in_chunk += gr->alpha_cb_size * | ||
122 | gr->pes_tpc_count[ppc_index][gpc_index]; | ||
123 | |||
124 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
125 | gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + temp + | ||
126 | proj_ppc_in_gpc_stride_v() * ppc_index, | ||
127 | gr->alpha_cb_default_size * gr->pes_tpc_count[ppc_index][gpc_index], | ||
128 | patch); | ||
129 | |||
130 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
131 | gr_gpcs_swdx_tc_beta_cb_size_r(ppc_index + gpc_index), | ||
132 | gr_gpcs_swdx_tc_beta_cb_size_v_f(cbm_cfg_size1), | ||
133 | patch); | ||
134 | } | ||
135 | } | ||
136 | |||
137 | if (patch) | ||
138 | gr_gk20a_ctx_patch_write_end(g, ch_ctx); | ||
139 | |||
140 | return 0; | ||
141 | } | ||
142 | |||
143 | void gr_gp10b_commit_global_pagepool(struct gk20a *g, | ||
144 | struct channel_ctx_gk20a *ch_ctx, | ||
145 | u64 addr, u32 size, bool patch) | ||
146 | { | ||
147 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_pagepool_base_r(), | ||
148 | gr_scc_pagepool_base_addr_39_8_f(addr), patch); | ||
149 | |||
150 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_pagepool_r(), | ||
151 | gr_scc_pagepool_total_pages_f(size) | | ||
152 | gr_scc_pagepool_valid_true_f(), patch); | ||
153 | |||
154 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_gcc_pagepool_base_r(), | ||
155 | gr_gpcs_gcc_pagepool_base_addr_39_8_f(addr), patch); | ||
156 | |||
157 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_gcc_pagepool_r(), | ||
158 | gr_gpcs_gcc_pagepool_total_pages_f(size), patch); | ||
159 | } | ||
160 | |||
50 | void gp10b_init_gr(struct gpu_ops *gops) | 161 | void gp10b_init_gr(struct gpu_ops *gops) |
51 | { | 162 | { |
52 | gm20b_init_gr(gops); | 163 | gm20b_init_gr(gops); |
53 | gops->gr.is_valid_class = gr_gp10b_is_valid_class; | 164 | gops->gr.is_valid_class = gr_gp10b_is_valid_class; |
165 | gops->gr.commit_global_cb_manager = gr_gp10b_commit_global_cb_manager; | ||
166 | gops->gr.commit_global_pagepool = gr_gp10b_commit_global_pagepool; | ||
54 | } | 167 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index f8607618..9b681104 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | |||
@@ -1362,7 +1362,7 @@ static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) | |||
1362 | { | 1362 | { |
1363 | return 0x4; | 1363 | return 0x4; |
1364 | } | 1364 | } |
1365 | static inline u32 gr_ds_tga_constraintlogic_r(void) | 1365 | static inline u32 gr_ds_tga_constraintlogic_beta_r(void) |
1366 | { | 1366 | { |
1367 | return 0x00405830; | 1367 | return 0x00405830; |
1368 | } | 1368 | } |
@@ -1370,7 +1370,7 @@ static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) | |||
1370 | { | 1370 | { |
1371 | return (v & 0x3fffff) << 0; | 1371 | return (v & 0x3fffff) << 0; |
1372 | } | 1372 | } |
1373 | static inline u32 gr_ds_tga_constraintlogic_r(void) | 1373 | static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) |
1374 | { | 1374 | { |
1375 | return 0x0040585c; | 1375 | return 0x0040585c; |
1376 | } | 1376 | } |
@@ -1926,6 +1926,10 @@ static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) | |||
1926 | { | 1926 | { |
1927 | return 0x005030f8; | 1927 | return 0x005030f8; |
1928 | } | 1928 | } |
1929 | static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) | ||
1930 | { | ||
1931 | return 0x005030f0; | ||
1932 | } | ||
1929 | static inline u32 gr_gpccs_falcon_addr_r(void) | 1933 | static inline u32 gr_gpccs_falcon_addr_r(void) |
1930 | { | 1934 | { |
1931 | return 0x0041a0ac; | 1935 | return 0x0041a0ac; |