2 files changed, 32 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 549a4da4..17685f59 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -695,6 +695,30 @@ void gr_gp10b_set_bes_crop_debug3(struct gk20a *g, u32 data)
         gk20a_writel(g, gr_bes_crop_debug3_r(), val);
 }
 
+void gr_gp10b_set_bes_crop_debug4(struct gk20a *g, u32 data)
+{
+        u32 val;
+
+        nvgpu_log_fn(g, " ");
+
+        val = gk20a_readl(g, gr_bes_crop_debug4_r());
+        if (data & NVC097_BES_CROP_DEBUG4_CLAMP_FP_BLEND_TO_MAXVAL) {
+                val = set_field(val,
+                        gr_bes_crop_debug4_clamp_fp_blend_m(),
+                        gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f());
+        } else if (data & NVC097_BES_CROP_DEBUG4_CLAMP_FP_BLEND_TO_INF) {
+                val = set_field(val,
+                        gr_bes_crop_debug4_clamp_fp_blend_m(),
+                        gr_bes_crop_debug4_clamp_fp_blend_to_inf_f());
+        } else {
+                nvgpu_warn(g,
+                        "gr_gp10b_set_bes_crop_debug4: wrong data sent!");
+                return;
+        }
+        gk20a_writel(g, gr_bes_crop_debug4_r(), val);
+}
+
+
 int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr,
                                      u32 class_num, u32 offset, u32 data)
 {
@@ -736,6 +760,9 @@ int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr,
                 case NVC097_SET_BES_CROP_DEBUG3:
                         g->ops.gr.set_bes_crop_debug3(g, data);
                         break;
+                case NVC097_SET_BES_CROP_DEBUG4:
+                        g->ops.gr.set_bes_crop_debug4(g, data);
+                        break;
                 default:
                         goto fail;
                 }
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
index 8d553d37..8f1ebb16 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
@@ -49,9 +49,13 @@ enum {
 #define NVC097_SET_CIRCULAR_BUFFER_SIZE         0x1280
 #define NVC097_SET_SHADER_EXCEPTIONS            0x1528
 #define NVC097_SET_BES_CROP_DEBUG3              0x10c4
+#define NVC097_SET_BES_CROP_DEBUG4              0x10b0
 #define NVC0C0_SET_SHADER_EXCEPTIONS            0x1528
 #define NVC0C0_SET_RD_COALESCE                  0x0228
 
+#define NVC097_BES_CROP_DEBUG4_CLAMP_FP_BLEND_TO_INF    0x0
+#define NVC097_BES_CROP_DEBUG4_CLAMP_FP_BLEND_TO_MAXVAL 0x1
+
 int gr_gp10b_init_fs_state(struct gk20a *g);
 int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size,
                         struct nvgpu_mem *mem);
@@ -85,6 +89,7 @@ int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
 u32 gr_gp10b_pagepool_default_size(struct gk20a *g);
 int gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g);
 void gr_gp10b_set_bes_crop_debug3(struct gk20a *g, u32 data);
+void gr_gp10b_set_bes_crop_debug4(struct gk20a *g, u32 data);
 int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr,
                                      u32 class_num, u32 offset, u32 data);
 void gr_gp10b_cb_size_default(struct gk20a *g);