diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ecc_gp10b.h | 41 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 27 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 4 |
4 files changed, 56 insertions, 42 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h b/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h new file mode 100644 index 00000000..454dcb20 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h | |||
@@ -0,0 +1,41 @@ | |||
1 | /* | ||
2 | * GP10B ECC | ||
3 | * | ||
4 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef _NVGPU_ECC_GP10B_H_ | ||
17 | #define _NVGPU_ECC_GP10B_H_ | ||
18 | |||
19 | #include <linux/version.h> | ||
20 | |||
21 | struct ecc_gr_t18x { | ||
22 | struct gk20a_ecc_stat sm_lrf_single_err_count; | ||
23 | struct gk20a_ecc_stat sm_lrf_double_err_count; | ||
24 | |||
25 | struct gk20a_ecc_stat sm_shm_sec_count; | ||
26 | struct gk20a_ecc_stat sm_shm_sed_count; | ||
27 | struct gk20a_ecc_stat sm_shm_ded_count; | ||
28 | |||
29 | struct gk20a_ecc_stat tex_total_sec_pipe0_count; | ||
30 | struct gk20a_ecc_stat tex_total_ded_pipe0_count; | ||
31 | struct gk20a_ecc_stat tex_unique_sec_pipe0_count; | ||
32 | struct gk20a_ecc_stat tex_unique_ded_pipe0_count; | ||
33 | struct gk20a_ecc_stat tex_total_sec_pipe1_count; | ||
34 | struct gk20a_ecc_stat tex_total_ded_pipe1_count; | ||
35 | struct gk20a_ecc_stat tex_unique_sec_pipe1_count; | ||
36 | struct gk20a_ecc_stat tex_unique_ded_pipe1_count; | ||
37 | |||
38 | struct gk20a_ecc_stat l2_sec_count; | ||
39 | struct gk20a_ecc_stat l2_ded_count; | ||
40 | }; | ||
41 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 1853aaec..2c85a667 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -169,7 +169,7 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
169 | lrf_ecc_ded_status, | 169 | lrf_ecc_ded_status, |
170 | &lrf_single_count_delta, | 170 | &lrf_single_count_delta, |
171 | lrf_double_count_delta); | 171 | lrf_double_count_delta); |
172 | g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters[tpc] += | 172 | g->ecc.gr.t18x.sm_lrf_single_err_count.counters[tpc] += |
173 | lrf_single_count_delta; | 173 | lrf_single_count_delta; |
174 | } | 174 | } |
175 | if (lrf_ecc_ded_status) { | 175 | if (lrf_ecc_ded_status) { |
@@ -181,7 +181,7 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
181 | lrf_ecc_ded_status, | 181 | lrf_ecc_ded_status, |
182 | &lrf_double_count_delta, | 182 | &lrf_double_count_delta, |
183 | lrf_single_count_delta); | 183 | lrf_single_count_delta); |
184 | g->gr.t18x.ecc_stats.sm_lrf_double_err_count.counters[tpc] += | 184 | g->ecc.gr.t18x.sm_lrf_double_err_count.counters[tpc] += |
185 | lrf_double_count_delta; | 185 | lrf_double_count_delta; |
186 | } | 186 | } |
187 | gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, | 187 | gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, |
@@ -206,9 +206,9 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
206 | ecc_stats_reg_val = | 206 | ecc_stats_reg_val = |
207 | gk20a_readl(g, | 207 | gk20a_readl(g, |
208 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); | 208 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); |
209 | g->gr.t18x.ecc_stats.sm_shm_sec_count.counters[tpc] += | 209 | g->ecc.gr.t18x.sm_shm_sec_count.counters[tpc] += |
210 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val); | 210 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val); |
211 | g->gr.t18x.ecc_stats.sm_shm_sed_count.counters[tpc] += | 211 | g->ecc.gr.t18x.sm_shm_sed_count.counters[tpc] += |
212 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val); | 212 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val); |
213 | ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() | | 213 | ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() | |
214 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m()); | 214 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m()); |
@@ -228,7 +228,7 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
228 | ecc_stats_reg_val = | 228 | ecc_stats_reg_val = |
229 | gk20a_readl(g, | 229 | gk20a_readl(g, |
230 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); | 230 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); |
231 | g->gr.t18x.ecc_stats.sm_shm_ded_count.counters[tpc] += | 231 | g->ecc.gr.t18x.sm_shm_ded_count.counters[tpc] += |
232 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val); | 232 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val); |
233 | ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m()); | 233 | ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m()); |
234 | gk20a_writel(g, | 234 | gk20a_writel(g, |
@@ -269,7 +269,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
269 | 269 | ||
270 | ecc_stats_reg_val = gk20a_readl(g, | 270 | ecc_stats_reg_val = gk20a_readl(g, |
271 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | 271 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); |
272 | g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count.counters[tpc] += | 272 | g->ecc.gr.t18x.tex_total_sec_pipe0_count.counters[tpc] += |
273 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); | 273 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); |
274 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); | 274 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); |
275 | gk20a_writel(g, | 275 | gk20a_writel(g, |
@@ -278,7 +278,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
278 | 278 | ||
279 | ecc_stats_reg_val = gk20a_readl(g, | 279 | ecc_stats_reg_val = gk20a_readl(g, |
280 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | 280 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); |
281 | g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count.counters[tpc] += | 281 | g->ecc.gr.t18x.tex_unique_sec_pipe0_count.counters[tpc] += |
282 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); | 282 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); |
283 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); | 283 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); |
284 | gk20a_writel(g, | 284 | gk20a_writel(g, |
@@ -293,7 +293,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
293 | 293 | ||
294 | ecc_stats_reg_val = gk20a_readl(g, | 294 | ecc_stats_reg_val = gk20a_readl(g, |
295 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | 295 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); |
296 | g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count.counters[tpc] += | 296 | g->ecc.gr.t18x.tex_total_sec_pipe1_count.counters[tpc] += |
297 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); | 297 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); |
298 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); | 298 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); |
299 | gk20a_writel(g, | 299 | gk20a_writel(g, |
@@ -302,7 +302,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
302 | 302 | ||
303 | ecc_stats_reg_val = gk20a_readl(g, | 303 | ecc_stats_reg_val = gk20a_readl(g, |
304 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | 304 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); |
305 | g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count.counters[tpc] += | 305 | g->ecc.gr.t18x.tex_unique_sec_pipe1_count.counters[tpc] += |
306 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); | 306 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); |
307 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); | 307 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); |
308 | gk20a_writel(g, | 308 | gk20a_writel(g, |
@@ -325,7 +325,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
325 | 325 | ||
326 | ecc_stats_reg_val = gk20a_readl(g, | 326 | ecc_stats_reg_val = gk20a_readl(g, |
327 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | 327 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); |
328 | g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count.counters[tpc] += | 328 | g->ecc.gr.t18x.tex_total_ded_pipe0_count.counters[tpc] += |
329 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); | 329 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); |
330 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); | 330 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); |
331 | gk20a_writel(g, | 331 | gk20a_writel(g, |
@@ -334,7 +334,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
334 | 334 | ||
335 | ecc_stats_reg_val = gk20a_readl(g, | 335 | ecc_stats_reg_val = gk20a_readl(g, |
336 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | 336 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); |
337 | g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count.counters[tpc] += | 337 | g->ecc.gr.t18x.tex_unique_ded_pipe0_count.counters[tpc] += |
338 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); | 338 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); |
339 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); | 339 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); |
340 | gk20a_writel(g, | 340 | gk20a_writel(g, |
@@ -349,7 +349,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
349 | 349 | ||
350 | ecc_stats_reg_val = gk20a_readl(g, | 350 | ecc_stats_reg_val = gk20a_readl(g, |
351 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | 351 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); |
352 | g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count.counters[tpc] += | 352 | g->ecc.gr.t18x.tex_total_ded_pipe1_count.counters[tpc] += |
353 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); | 353 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); |
354 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); | 354 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); |
355 | gk20a_writel(g, | 355 | gk20a_writel(g, |
@@ -358,7 +358,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
358 | 358 | ||
359 | ecc_stats_reg_val = gk20a_readl(g, | 359 | ecc_stats_reg_val = gk20a_readl(g, |
360 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | 360 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); |
361 | g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count.counters[tpc] += | 361 | g->ecc.gr.t18x.tex_unique_ded_pipe1_count.counters[tpc] += |
362 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); | 362 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); |
363 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); | 363 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); |
364 | gk20a_writel(g, | 364 | gk20a_writel(g, |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index 588a7d8f..81ec7927 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h | |||
@@ -22,12 +22,6 @@ | |||
22 | 22 | ||
23 | struct gpu_ops; | 23 | struct gpu_ops; |
24 | 24 | ||
25 | struct gr_gp10b_ecc_stat { | ||
26 | char **names; | ||
27 | u32 *counters; | ||
28 | struct hlist_node hash_node; | ||
29 | }; | ||
30 | |||
31 | enum { | 25 | enum { |
32 | PASCAL_CHANNEL_GPFIFO_A = 0xC06F, | 26 | PASCAL_CHANNEL_GPFIFO_A = 0xC06F, |
33 | PASCAL_A = 0xC097, | 27 | PASCAL_A = 0xC097, |
@@ -68,27 +62,6 @@ struct gr_t18x { | |||
68 | struct dentry *debugfs_dump_ctxsw_stats; | 62 | struct dentry *debugfs_dump_ctxsw_stats; |
69 | } ctx_vars; | 63 | } ctx_vars; |
70 | 64 | ||
71 | struct { | ||
72 | struct gr_gp10b_ecc_stat sm_lrf_single_err_count; | ||
73 | struct gr_gp10b_ecc_stat sm_lrf_double_err_count; | ||
74 | |||
75 | struct gr_gp10b_ecc_stat sm_shm_sec_count; | ||
76 | struct gr_gp10b_ecc_stat sm_shm_sed_count; | ||
77 | struct gr_gp10b_ecc_stat sm_shm_ded_count; | ||
78 | |||
79 | struct gr_gp10b_ecc_stat tex_total_sec_pipe0_count; | ||
80 | struct gr_gp10b_ecc_stat tex_total_ded_pipe0_count; | ||
81 | struct gr_gp10b_ecc_stat tex_unique_sec_pipe0_count; | ||
82 | struct gr_gp10b_ecc_stat tex_unique_ded_pipe0_count; | ||
83 | struct gr_gp10b_ecc_stat tex_total_sec_pipe1_count; | ||
84 | struct gr_gp10b_ecc_stat tex_total_ded_pipe1_count; | ||
85 | struct gr_gp10b_ecc_stat tex_unique_sec_pipe1_count; | ||
86 | struct gr_gp10b_ecc_stat tex_unique_ded_pipe1_count; | ||
87 | |||
88 | struct gr_gp10b_ecc_stat l2_sec_count; | ||
89 | struct gr_gp10b_ecc_stat l2_ded_count; | ||
90 | } ecc_stats; | ||
91 | |||
92 | u32 fecs_feature_override_ecc_val; | 65 | u32 fecs_feature_override_ecc_val; |
93 | 66 | ||
94 | int cilp_preempt_pending_chid; | 67 | int cilp_preempt_pending_chid; |
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index e65e3d06..165e93fe 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | |||
@@ -149,7 +149,7 @@ static void gp10b_ltc_isr(struct gk20a *g) | |||
149 | ecc_stats_reg_val = | 149 | ecc_stats_reg_val = |
150 | gk20a_readl(g, | 150 | gk20a_readl(g, |
151 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset); | 151 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset); |
152 | g->gr.t18x.ecc_stats.l2_sec_count.counters[ltc] += | 152 | g->ecc.gr.t18x.l2_sec_count.counters[ltc] += |
153 | ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val); | 153 | ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val); |
154 | ecc_stats_reg_val &= | 154 | ecc_stats_reg_val &= |
155 | ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m()); | 155 | ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m()); |
@@ -169,7 +169,7 @@ static void gp10b_ltc_isr(struct gk20a *g) | |||
169 | ecc_stats_reg_val = | 169 | ecc_stats_reg_val = |
170 | gk20a_readl(g, | 170 | gk20a_readl(g, |
171 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset); | 171 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset); |
172 | g->gr.t18x.ecc_stats.l2_ded_count.counters[ltc] += | 172 | g->ecc.gr.t18x.l2_ded_count.counters[ltc] += |
173 | ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val); | 173 | ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val); |
174 | ecc_stats_reg_val &= | 174 | ecc_stats_reg_val &= |
175 | ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m()); | 175 | ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m()); |