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Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/therm_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/therm_gp10b.c141
1 files changed, 141 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c
new file mode 100644
index 00000000..e02259d8
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c
@@ -0,0 +1,141 @@
1/*
2 * GP10B Therm
3 *
4 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include "gk20a/gk20a.h"
26#include "therm_gp10b.h"
27
28#include <nvgpu/soc.h>
29
30#include <nvgpu/hw/gp10b/hw_therm_gp10b.h>
31
32int gp10b_init_therm_setup_hw(struct gk20a *g)
33{
34 u32 v;
35
36 gk20a_dbg_fn("");
37
38 /* program NV_THERM registers */
39 gk20a_writel(g, therm_use_a_r(), therm_use_a_ext_therm_0_enable_f() |
40 therm_use_a_ext_therm_1_enable_f() |
41 therm_use_a_ext_therm_2_enable_f());
42 gk20a_writel(g, therm_evt_ext_therm_0_r(),
43 therm_evt_ext_therm_0_slow_factor_f(0x2));
44 gk20a_writel(g, therm_evt_ext_therm_1_r(),
45 therm_evt_ext_therm_1_slow_factor_f(0x6));
46 gk20a_writel(g, therm_evt_ext_therm_2_r(),
47 therm_evt_ext_therm_2_slow_factor_f(0xe));
48
49 gk20a_writel(g, therm_grad_stepping_table_r(0),
50 therm_grad_stepping_table_slowdown_factor0_f(
51 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f()) |
52 therm_grad_stepping_table_slowdown_factor1_f(
53 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f()) |
54 therm_grad_stepping_table_slowdown_factor2_f(
55 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f()) |
56 therm_grad_stepping_table_slowdown_factor3_f(
57 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
58 therm_grad_stepping_table_slowdown_factor4_f(
59 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
60
61 gk20a_writel(g, therm_grad_stepping_table_r(1),
62 therm_grad_stepping_table_slowdown_factor0_f(
63 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
64 therm_grad_stepping_table_slowdown_factor1_f(
65 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
66 therm_grad_stepping_table_slowdown_factor2_f(
67 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
68 therm_grad_stepping_table_slowdown_factor3_f(
69 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
70 therm_grad_stepping_table_slowdown_factor4_f(
71 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
72
73 v = gk20a_readl(g, therm_clk_timing_r(0));
74 v |= therm_clk_timing_grad_slowdown_enabled_f();
75 gk20a_writel(g, therm_clk_timing_r(0), v);
76
77 v = gk20a_readl(g, therm_config2_r());
78 v |= therm_config2_grad_enable_f(1);
79 v |= therm_config2_slowdown_factor_extended_f(1);
80 gk20a_writel(g, therm_config2_r(), v);
81
82 gk20a_writel(g, therm_grad_stepping1_r(),
83 therm_grad_stepping1_pdiv_duration_f(32));
84
85 v = gk20a_readl(g, therm_grad_stepping0_r());
86 v |= therm_grad_stepping0_feature_enable_f();
87 gk20a_writel(g, therm_grad_stepping0_r(), v);
88
89 return 0;
90}
91
92int gp10b_elcg_init_idle_filters(struct gk20a *g)
93{
94 u32 gate_ctrl, idle_filter;
95 u32 engine_id;
96 u32 active_engine_id = 0;
97 struct fifo_gk20a *f = &g->fifo;
98
99 gk20a_dbg_fn("");
100
101 for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
102 active_engine_id = f->active_engines_list[engine_id];
103 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
104
105 if (nvgpu_platform_is_simulation(g)) {
106 gate_ctrl = set_field(gate_ctrl,
107 therm_gate_ctrl_eng_delay_after_m(),
108 therm_gate_ctrl_eng_delay_after_f(4));
109 }
110
111 /* 2 * (1 << 9) = 1024 clks */
112 gate_ctrl = set_field(gate_ctrl,
113 therm_gate_ctrl_eng_idle_filt_exp_m(),
114 therm_gate_ctrl_eng_idle_filt_exp_f(9));
115 gate_ctrl = set_field(gate_ctrl,
116 therm_gate_ctrl_eng_idle_filt_mant_m(),
117 therm_gate_ctrl_eng_idle_filt_mant_f(2));
118 gate_ctrl = set_field(gate_ctrl,
119 therm_gate_ctrl_eng_delay_before_m(),
120 therm_gate_ctrl_eng_delay_before_f(4));
121 gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
122 }
123
124 /* default fecs_idle_filter to 0 */
125 idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
126 idle_filter &= ~therm_fecs_idle_filter_value_m();
127 gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
128 /* default hubmmu_idle_filter to 0 */
129 idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
130 idle_filter &= ~therm_hubmmu_idle_filter_value_m();
131 gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
132
133 gk20a_dbg_fn("done");
134 return 0;
135}
136
137void gp10b_init_therm_ops(struct gpu_ops *gops)
138{
139 gops->therm.init_therm_setup_hw = gp10b_init_therm_setup_hw;
140 gops->therm.elcg_init_idle_filters = gp10b_elcg_init_idle_filters;
141}
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