diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index c94d580a..ca111725 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -37,8 +37,8 @@ | |||
37 | #include <nvgpu/hw/gp10b/hw_pwr_gp10b.h> | 37 | #include <nvgpu/hw/gp10b/hw_pwr_gp10b.h> |
38 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | 38 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> |
39 | 39 | ||
40 | #define gp10b_dbg_pmu(fmt, arg...) \ | 40 | #define gp10b_dbg_pmu(g, fmt, arg...) \ |
41 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) | 41 | nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg) |
42 | 42 | ||
43 | /* PROD settings for ELPG sequencing registers*/ | 43 | /* PROD settings for ELPG sequencing registers*/ |
44 | static struct pg_init_sequence_list _pginitseq_gp10b[] = { | 44 | static struct pg_init_sequence_list _pginitseq_gp10b[] = { |
@@ -147,9 +147,9 @@ static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, | |||
147 | struct pmu_cmd cmd; | 147 | struct pmu_cmd cmd; |
148 | u32 seq; | 148 | u32 seq; |
149 | 149 | ||
150 | gk20a_dbg_fn(""); | 150 | nvgpu_log_fn(g, " "); |
151 | 151 | ||
152 | gp10b_dbg_pmu("wprinit status = %x\n", g->pmu_lsf_pmu_wpr_init_done); | 152 | gp10b_dbg_pmu(g, "wprinit status = %x\n", g->pmu_lsf_pmu_wpr_init_done); |
153 | if (g->pmu_lsf_pmu_wpr_init_done) { | 153 | if (g->pmu_lsf_pmu_wpr_init_done) { |
154 | /* send message to load FECS falcon */ | 154 | /* send message to load FECS falcon */ |
155 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | 155 | memset(&cmd, 0, sizeof(struct pmu_cmd)); |
@@ -164,13 +164,13 @@ static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, | |||
164 | cmd.cmd.acr.boot_falcons.usevamask = 0; | 164 | cmd.cmd.acr.boot_falcons.usevamask = 0; |
165 | cmd.cmd.acr.boot_falcons.wprvirtualbase.lo = 0x0; | 165 | cmd.cmd.acr.boot_falcons.wprvirtualbase.lo = 0x0; |
166 | cmd.cmd.acr.boot_falcons.wprvirtualbase.hi = 0x0; | 166 | cmd.cmd.acr.boot_falcons.wprvirtualbase.hi = 0x0; |
167 | gp10b_dbg_pmu("PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n", | 167 | gp10b_dbg_pmu(g, "PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n", |
168 | falconidmask); | 168 | falconidmask); |
169 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 169 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
170 | pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0); | 170 | pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0); |
171 | } | 171 | } |
172 | 172 | ||
173 | gk20a_dbg_fn("done"); | 173 | nvgpu_log_fn(g, "done"); |
174 | return; | 174 | return; |
175 | } | 175 | } |
176 | 176 | ||
@@ -209,7 +209,7 @@ int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) | |||
209 | static void pmu_handle_gr_param_msg(struct gk20a *g, struct pmu_msg *msg, | 209 | static void pmu_handle_gr_param_msg(struct gk20a *g, struct pmu_msg *msg, |
210 | void *param, u32 handle, u32 status) | 210 | void *param, u32 handle, u32 status) |
211 | { | 211 | { |
212 | gk20a_dbg_fn(""); | 212 | nvgpu_log_fn(g, " "); |
213 | 213 | ||
214 | if (status != 0) { | 214 | if (status != 0) { |
215 | nvgpu_err(g, "GR PARAM cmd aborted"); | 215 | nvgpu_err(g, "GR PARAM cmd aborted"); |
@@ -217,7 +217,7 @@ static void pmu_handle_gr_param_msg(struct gk20a *g, struct pmu_msg *msg, | |||
217 | return; | 217 | return; |
218 | } | 218 | } |
219 | 219 | ||
220 | gp10b_dbg_pmu("GR PARAM is acknowledged from PMU %x \n", | 220 | gp10b_dbg_pmu(g, "GR PARAM is acknowledged from PMU %x \n", |
221 | msg->msg.pg.msg_type); | 221 | msg->msg.pg.msg_type); |
222 | 222 | ||
223 | return; | 223 | return; |
@@ -243,7 +243,7 @@ int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) | |||
243 | cmd.cmd.pg.gr_init_param_v2.ldiv_slowdown_factor = | 243 | cmd.cmd.pg.gr_init_param_v2.ldiv_slowdown_factor = |
244 | g->ldiv_slowdown_factor; | 244 | g->ldiv_slowdown_factor; |
245 | 245 | ||
246 | gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM "); | 246 | gp10b_dbg_pmu(g, "cmd post PMU_PG_CMD_ID_PG_PARAM "); |
247 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 247 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
248 | pmu_handle_gr_param_msg, pmu, &seq, ~0); | 248 | pmu_handle_gr_param_msg, pmu, &seq, ~0); |
249 | 249 | ||
@@ -276,7 +276,7 @@ int gp10b_pmu_setup_elpg(struct gk20a *g) | |||
276 | u32 reg_writes; | 276 | u32 reg_writes; |
277 | u32 index; | 277 | u32 index; |
278 | 278 | ||
279 | gk20a_dbg_fn(""); | 279 | nvgpu_log_fn(g, " "); |
280 | 280 | ||
281 | if (g->elpg_enabled) { | 281 | if (g->elpg_enabled) { |
282 | reg_writes = ((sizeof(_pginitseq_gp10b) / | 282 | reg_writes = ((sizeof(_pginitseq_gp10b) / |
@@ -288,7 +288,7 @@ int gp10b_pmu_setup_elpg(struct gk20a *g) | |||
288 | } | 288 | } |
289 | } | 289 | } |
290 | 290 | ||
291 | gk20a_dbg_fn("done"); | 291 | nvgpu_log_fn(g, "done"); |
292 | return ret; | 292 | return ret; |
293 | } | 293 | } |
294 | 294 | ||
@@ -305,7 +305,7 @@ int gp10b_init_pmu_setup_hw1(struct gk20a *g) | |||
305 | struct nvgpu_pmu *pmu = &g->pmu; | 305 | struct nvgpu_pmu *pmu = &g->pmu; |
306 | int err; | 306 | int err; |
307 | 307 | ||
308 | gk20a_dbg_fn(""); | 308 | nvgpu_log_fn(g, " "); |
309 | 309 | ||
310 | nvgpu_mutex_acquire(&pmu->isr_mutex); | 310 | nvgpu_mutex_acquire(&pmu->isr_mutex); |
311 | nvgpu_flcn_reset(pmu->flcn); | 311 | nvgpu_flcn_reset(pmu->flcn); |
@@ -333,7 +333,7 @@ int gp10b_init_pmu_setup_hw1(struct gk20a *g) | |||
333 | if (err) | 333 | if (err) |
334 | return err; | 334 | return err; |
335 | 335 | ||
336 | gk20a_dbg_fn("done"); | 336 | nvgpu_log_fn(g, "done"); |
337 | return 0; | 337 | return 0; |
338 | 338 | ||
339 | } | 339 | } |