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path: root/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/pmu_gp10b.c39
1 files changed, 0 insertions, 39 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
index 5c7d1523..d268ab88 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
@@ -304,45 +304,6 @@ void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr)
304 0x0); 304 0x0);
305} 305}
306 306
307int gp10b_init_pmu_setup_hw1(struct gk20a *g)
308{
309 struct nvgpu_pmu *pmu = &g->pmu;
310 int err;
311
312 nvgpu_log_fn(g, " ");
313
314 nvgpu_mutex_acquire(&pmu->isr_mutex);
315 nvgpu_flcn_reset(pmu->flcn);
316 pmu->isr_enabled = true;
317 nvgpu_mutex_release(&pmu->isr_mutex);
318
319 /* setup apertures - virtual */
320 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
321 pwr_fbif_transcfg_mem_type_virtual_f());
322 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
323 pwr_fbif_transcfg_mem_type_virtual_f());
324
325 /* setup apertures - physical */
326 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
327 pwr_fbif_transcfg_mem_type_physical_f() |
328 pwr_fbif_transcfg_target_local_fb_f());
329 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
330 pwr_fbif_transcfg_mem_type_physical_f() |
331 pwr_fbif_transcfg_target_coherent_sysmem_f());
332 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
333 pwr_fbif_transcfg_mem_type_physical_f() |
334 pwr_fbif_transcfg_target_noncoherent_sysmem_f());
335
336 err = g->ops.pmu.pmu_nsbootstrap(pmu);
337 if (err) {
338 return err;
339 }
340
341 nvgpu_log_fn(g, "done");
342 return 0;
343
344}
345
346bool gp10b_is_lazy_bootstrap(u32 falcon_id) 307bool gp10b_is_lazy_bootstrap(u32 falcon_id)
347{ 308{
348 bool enable_status = false; 309 bool enable_status = false;