summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/pmu_gp10b.c493
1 files changed, 493 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
new file mode 100644
index 00000000..12337934
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
@@ -0,0 +1,493 @@
1/*
2 * GP10B PMU
3 *
4 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/delay.h> /* for udelay */
17#include <linux/tegra-fuse.h>
18#include "gk20a/gk20a.h"
19#include "gk20a/pmu_gk20a.h"
20#include "gm20b/acr_gm20b.h"
21#include "gm20b/pmu_gm20b.h"
22
23#include "pmu_gp10b.h"
24#include "hw_pwr_gp10b.h"
25#include "hw_fuse_gp10b.h"
26#include "gp10b_sysfs.h"
27
28#define gp10b_dbg_pmu(fmt, arg...) \
29 gk20a_dbg(gpu_dbg_pmu, fmt, ##arg)
30/*!
31 * Structure/object which single register write need to be done during PG init
32 * sequence to set PROD values.
33 */
34struct pg_init_sequence_list {
35 u32 regaddr;
36 u32 writeval;
37};
38
39/* PROD settings for ELPG sequencing registers*/
40static struct pg_init_sequence_list _pginitseq_gp10b[] = {
41 {0x0010ab10, 0x0000868B} ,
42 {0x0010e118, 0x8590848F} ,
43 {0x0010e000, 0} ,
44 {0x0010e06c, 0x000000A3} ,
45 {0x0010e06c, 0x000000A0} ,
46 {0x0010e06c, 0x00000095} ,
47 {0x0010e06c, 0x000000A6} ,
48 {0x0010e06c, 0x0000008C} ,
49 {0x0010e06c, 0x00000080} ,
50 {0x0010e06c, 0x00000081} ,
51 {0x0010e06c, 0x00000087} ,
52 {0x0010e06c, 0x00000088} ,
53 {0x0010e06c, 0x0000008D} ,
54 {0x0010e06c, 0x00000082} ,
55 {0x0010e06c, 0x00000083} ,
56 {0x0010e06c, 0x00000089} ,
57 {0x0010e06c, 0x0000008A} ,
58 {0x0010e06c, 0x000000A2} ,
59 {0x0010e06c, 0x00000097} ,
60 {0x0010e06c, 0x00000092} ,
61 {0x0010e06c, 0x00000099} ,
62 {0x0010e06c, 0x0000009B} ,
63 {0x0010e06c, 0x0000009D} ,
64 {0x0010e06c, 0x0000009F} ,
65 {0x0010e06c, 0x000000A1} ,
66 {0x0010e06c, 0x00000096} ,
67 {0x0010e06c, 0x00000091} ,
68 {0x0010e06c, 0x00000098} ,
69 {0x0010e06c, 0x0000009A} ,
70 {0x0010e06c, 0x0000009C} ,
71 {0x0010e06c, 0x0000009E} ,
72 {0x0010ab14, 0x00000000} ,
73 {0x0010e024, 0x00000000} ,
74 {0x0010e028, 0x00000000} ,
75 {0x0010e11c, 0x00000000} ,
76 {0x0010ab1c, 0x140B0BFF} ,
77 {0x0010e020, 0x0E2626FF} ,
78 {0x0010e124, 0x251010FF} ,
79 {0x0010ab20, 0x89abcdef} ,
80 {0x0010ab24, 0x00000000} ,
81 {0x0010e02c, 0x89abcdef} ,
82 {0x0010e030, 0x00000000} ,
83 {0x0010e128, 0x89abcdef} ,
84 {0x0010e12c, 0x00000000} ,
85 {0x0010ab28, 0x7FFFFFFF} ,
86 {0x0010ab2c, 0x70000000} ,
87 {0x0010e034, 0x7FFFFFFF} ,
88 {0x0010e038, 0x70000000} ,
89 {0x0010e130, 0x7FFFFFFF} ,
90 {0x0010e134, 0x70000000} ,
91 {0x0010ab30, 0x00000000} ,
92 {0x0010ab34, 0x00000001} ,
93 {0x00020004, 0x00000000} ,
94 {0x0010e138, 0x00000000} ,
95 {0x0010e040, 0x00000000} ,
96 {0x0010e168, 0x00000000} ,
97 {0x0010e114, 0x0000A5A4} ,
98 {0x0010e110, 0x00000000} ,
99 {0x0010e10c, 0x8590848F} ,
100 {0x0010e05c, 0x00000000} ,
101 {0x0010e044, 0x00000000} ,
102 {0x0010a644, 0x0000868B} ,
103 {0x0010a648, 0x00000000} ,
104 {0x0010a64c, 0x00829493} ,
105 {0x0010a650, 0x00000000} ,
106 {0x0010e000, 0} ,
107 {0x0010e068, 0x000000A3} ,
108 {0x0010e068, 0x000000A0} ,
109 {0x0010e068, 0x00000095} ,
110 {0x0010e068, 0x000000A6} ,
111 {0x0010e068, 0x0000008C} ,
112 {0x0010e068, 0x00000080} ,
113 {0x0010e068, 0x00000081} ,
114 {0x0010e068, 0x00000087} ,
115 {0x0010e068, 0x00000088} ,
116 {0x0010e068, 0x0000008D} ,
117 {0x0010e068, 0x00000082} ,
118 {0x0010e068, 0x00000083} ,
119 {0x0010e068, 0x00000089} ,
120 {0x0010e068, 0x0000008A} ,
121 {0x0010e068, 0x000000A2} ,
122 {0x0010e068, 0x00000097} ,
123 {0x0010e068, 0x00000092} ,
124 {0x0010e068, 0x00000099} ,
125 {0x0010e068, 0x0000009B} ,
126 {0x0010e068, 0x0000009D} ,
127 {0x0010e068, 0x0000009F} ,
128 {0x0010e068, 0x000000A1} ,
129 {0x0010e068, 0x00000096} ,
130 {0x0010e068, 0x00000091} ,
131 {0x0010e068, 0x00000098} ,
132 {0x0010e068, 0x0000009A} ,
133 {0x0010e068, 0x0000009C} ,
134 {0x0010e068, 0x0000009E} ,
135 {0x0010e000, 0} ,
136 {0x0010e004, 0x0000008E},
137};
138
139static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask,
140 u32 flags)
141{
142 struct pmu_gk20a *pmu = &g->pmu;
143 struct pmu_cmd cmd;
144 u32 seq;
145
146 gk20a_dbg_fn("");
147
148 gp10b_dbg_pmu("wprinit status = %x\n", g->ops.pmu.lspmuwprinitdone);
149 if (g->ops.pmu.lspmuwprinitdone) {
150 /* send message to load FECS falcon */
151 memset(&cmd, 0, sizeof(struct pmu_cmd));
152 cmd.hdr.unit_id = PMU_UNIT_ACR;
153 cmd.hdr.size = PMU_CMD_HDR_SIZE +
154 sizeof(struct pmu_acr_cmd_bootstrap_multiple_falcons);
155 cmd.cmd.acr.boot_falcons.cmd_type =
156 PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS;
157 cmd.cmd.acr.boot_falcons.flags = flags;
158 cmd.cmd.acr.boot_falcons.falconidmask =
159 falconidmask;
160 cmd.cmd.acr.boot_falcons.usevamask = 0;
161 cmd.cmd.acr.boot_falcons.wprvirtualbase.lo =
162 u64_lo32(g->pmu.wpr_buf.gpu_va);
163 cmd.cmd.acr.boot_falcons.wprvirtualbase.hi =
164 u64_hi32(g->pmu.wpr_buf.gpu_va);
165 gp10b_dbg_pmu("PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n",
166 falconidmask);
167 gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
168 pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0);
169 }
170
171 gk20a_dbg_fn("done");
172 return;
173}
174
175int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
176{
177 u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES;
178
179 /* GM20B PMU supports loading FECS and GPCCS only */
180 if (falconidmask == 0)
181 return -EINVAL;
182 if (falconidmask & ~((1 << LSF_FALCON_ID_FECS) |
183 (1 << LSF_FALCON_ID_GPCCS)))
184 return -EINVAL;
185 g->ops.pmu.lsfloadedfalconid = 0;
186 /* check whether pmu is ready to bootstrap lsf if not wait for it */
187 if (!g->ops.pmu.lspmuwprinitdone) {
188 pmu_wait_message_cond(&g->pmu,
189 gk20a_get_gr_idle_timeout(g),
190 &g->ops.pmu.lspmuwprinitdone, 1);
191 /* check again if it still not ready indicate an error */
192 if (!g->ops.pmu.lspmuwprinitdone) {
193 gk20a_err(dev_from_gk20a(g),
194 "PMU not ready to load LSF");
195 return -ETIMEDOUT;
196 }
197 }
198 /* load falcon(s) */
199 gp10b_pmu_load_multiple_falcons(g, falconidmask, flags);
200 pmu_wait_message_cond(&g->pmu,
201 gk20a_get_gr_idle_timeout(g),
202 &g->ops.pmu.lsfloadedfalconid, falconidmask);
203 if (g->ops.pmu.lsfloadedfalconid != falconidmask)
204 return -ETIMEDOUT;
205 return 0;
206}
207
208static void pmu_handle_gr_param_msg(struct gk20a *g, struct pmu_msg *msg,
209 void *param, u32 handle, u32 status)
210{
211 gk20a_dbg_fn("");
212
213 if (status != 0) {
214 gk20a_err(dev_from_gk20a(g), "GR PARAM cmd aborted");
215 /* TBD: disable ELPG */
216 return;
217 }
218
219 gp10b_dbg_pmu("GR PARAM is acknowledged from PMU %x \n",
220 msg->msg.pg.msg_type);
221
222 return;
223}
224
225int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id)
226{
227 struct pmu_gk20a *pmu = &g->pmu;
228 struct pmu_cmd cmd;
229 u32 seq;
230
231 if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) {
232 memset(&cmd, 0, sizeof(struct pmu_cmd));
233 cmd.hdr.unit_id = PMU_UNIT_PG;
234 cmd.hdr.size = PMU_CMD_HDR_SIZE +
235 sizeof(struct pmu_pg_cmd_gr_init_param);
236 cmd.cmd.pg.gr_init_param.cmd_type =
237 PMU_PG_CMD_ID_PG_PARAM;
238 cmd.cmd.pg.gr_init_param.sub_cmd_id =
239 PMU_PG_PARAM_CMD_GR_INIT_PARAM;
240 cmd.cmd.pg.gr_init_param.featuremask =
241 PMU_PG_FEATURE_GR_POWER_GATING_ENABLED;
242
243 gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM ");
244 gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
245 pmu_handle_gr_param_msg, pmu, &seq, ~0);
246
247 } else
248 return -EINVAL;
249
250 return 0;
251}
252
253void gp10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
254 u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt)
255{
256 struct pmu_gk20a *pmu = &g->pmu;
257 struct pmu_pg_stats_v1 stats;
258
259 pmu_copy_from_dmem(pmu,
260 pmu->stat_dmem_offset[pg_engine_id],
261 (u8 *)&stats, sizeof(struct pmu_pg_stats_v1), 0);
262
263 *ingating_time = stats.total_sleep_timeus;
264 *ungating_time = stats.total_nonsleep_timeus;
265 *gating_cnt = stats.entry_count;
266}
267
268static int gp10b_pmu_setup_elpg(struct gk20a *g)
269{
270 int ret = 0;
271 u32 reg_writes;
272 u32 index;
273
274 gk20a_dbg_fn("");
275
276 if (g->elpg_enabled) {
277 reg_writes = ((sizeof(_pginitseq_gp10b) /
278 sizeof((_pginitseq_gp10b)[0])));
279 /* Initialize registers with production values*/
280 for (index = 0; index < reg_writes; index++) {
281 gk20a_writel(g, _pginitseq_gp10b[index].regaddr,
282 _pginitseq_gp10b[index].writeval);
283 }
284 }
285
286 gk20a_dbg_fn("done");
287 return ret;
288}
289
290void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr)
291{
292 gk20a_writel(g, pwr_falcon_dmatrfbase_r(),
293 addr);
294 gk20a_writel(g, pwr_falcon_dmatrfbase1_r(),
295 0x0);
296}
297
298static int gp10b_init_pmu_setup_hw1(struct gk20a *g)
299{
300 struct pmu_gk20a *pmu = &g->pmu;
301 int err;
302
303 gk20a_dbg_fn("");
304
305 mutex_lock(&pmu->isr_mutex);
306 pmu_reset(pmu);
307 pmu->isr_enabled = true;
308 mutex_unlock(&pmu->isr_mutex);
309
310 /* setup apertures - virtual */
311 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
312 pwr_fbif_transcfg_mem_type_virtual_f());
313 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
314 pwr_fbif_transcfg_mem_type_virtual_f());
315
316 /* setup apertures - physical */
317 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
318 pwr_fbif_transcfg_mem_type_physical_f() |
319 pwr_fbif_transcfg_target_local_fb_f());
320 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
321 pwr_fbif_transcfg_mem_type_physical_f() |
322 pwr_fbif_transcfg_target_coherent_sysmem_f());
323 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
324 pwr_fbif_transcfg_mem_type_physical_f() |
325 pwr_fbif_transcfg_target_noncoherent_sysmem_f());
326
327 err = pmu_bootstrap(pmu);
328 if (err)
329 return err;
330
331 gk20a_dbg_fn("done");
332 return 0;
333
334}
335
336static void pmu_handle_ecc_en_dis_msg(struct gk20a *g, struct pmu_msg *msg,
337 void *param, u32 handle, u32 status)
338{
339 struct pmu_gk20a *pmu = &g->pmu;
340 struct pmu_msg_lrf_tex_ltc_dram_en_dis *ecc =
341 &msg->msg.lrf_tex_ltc_dram.en_dis;
342 gk20a_dbg_fn("");
343
344 if (status != 0) {
345 gk20a_err(dev_from_gk20a(g), "ECC en dis cmd aborted");
346 return;
347 }
348 if (msg->msg.lrf_tex_ltc_dram.msg_type !=
349 PMU_LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS) {
350 gk20a_err(dev_from_gk20a(g),
351 "Invalid msg for LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS cmd");
352 return;
353 } else if (ecc->pmu_status != 0) {
354 gk20a_err(dev_from_gk20a(g),
355 "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg status = %x",
356 ecc->pmu_status);
357 gk20a_err(dev_from_gk20a(g),
358 "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg en fail = %x",
359 ecc->en_fail_mask);
360 gk20a_err(dev_from_gk20a(g),
361 "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg dis fail = %x",
362 ecc->dis_fail_mask);
363 } else
364 pmu->override_done = 1;
365 gk20a_dbg_fn("done");
366}
367
368static int send_ecc_overide_en_dis_cmd(struct gk20a *g, u32 bitmask)
369{
370 struct pmu_gk20a *pmu = &g->pmu;
371 struct pmu_cmd cmd;
372 u32 seq;
373 int status;
374 u32 val;
375 gk20a_dbg_fn("");
376
377 tegra_fuse_readl(FUSE_OPT_ECC_EN, &val);
378 if (!val) {
379 gk20a_err(dev_from_gk20a(g), "Board not ECC capable");
380 return -1;
381 }
382 if (!(g->acr.capabilities &
383 ACR_LRF_TEX_LTC_DRAM_PRIV_MASK_ENABLE_LS_OVERRIDE)) {
384 gk20a_err(dev_from_gk20a(g), "check ACR capabilities");
385 return -1;
386 }
387 memset(&cmd, 0, sizeof(struct pmu_cmd));
388 cmd.hdr.unit_id = PMU_UNIT_FECS_MEM_OVERRIDE;
389 cmd.hdr.size = PMU_CMD_HDR_SIZE +
390 sizeof(struct pmu_cmd_lrf_tex_ltc_dram_en_dis);
391 cmd.cmd.lrf_tex_ltc_dram.en_dis.cmd_type =
392 PMU_LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS;
393 cmd.cmd.lrf_tex_ltc_dram.en_dis.en_dis_mask = (u8)(bitmask & 0xff);
394
395 gp10b_dbg_pmu("cmd post PMU_ECC_CMD_ID_EN_DIS_ECC");
396 pmu->override_done = 0;
397 status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ,
398 pmu_handle_ecc_en_dis_msg, NULL, &seq, ~0);
399 if (status)
400 gk20a_err(dev_from_gk20a(g), "ECC override failed");
401 else
402 pmu_wait_message_cond(pmu, gk20a_get_gr_idle_timeout(g),
403 &pmu->override_done, 1);
404 gk20a_dbg_fn("done");
405 return status;
406}
407
408static bool gp10b_is_lazy_bootstrap(u32 falcon_id)
409{
410 bool enable_status = false;
411
412 switch (falcon_id) {
413 case LSF_FALCON_ID_FECS:
414 enable_status = false;
415 break;
416 case LSF_FALCON_ID_GPCCS:
417 enable_status = true;
418 break;
419 default:
420 break;
421 }
422
423 return enable_status;
424}
425
426static bool gp10b_is_priv_load(u32 falcon_id)
427{
428 bool enable_status = false;
429
430 switch (falcon_id) {
431 case LSF_FALCON_ID_FECS:
432 enable_status = false;
433 break;
434 case LSF_FALCON_ID_GPCCS:
435 enable_status = true;
436 break;
437 default:
438 break;
439 }
440
441 return enable_status;
442}
443
444/*Dump Security related fuses*/
445static void pmu_dump_security_fuses_gp10b(struct gk20a *g)
446{
447 u32 val;
448
449 gk20a_err(dev_from_gk20a(g), "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x",
450 gk20a_readl(g, fuse_opt_sec_debug_en_r()));
451 gk20a_err(dev_from_gk20a(g), "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x",
452 gk20a_readl(g, fuse_opt_priv_sec_en_r()));
453 tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val);
454 gk20a_err(dev_from_gk20a(g), "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x",
455 val);
456}
457
458static bool gp10b_is_pmu_supported(struct gk20a *g)
459{
460 return true;
461}
462
463void gp10b_init_pmu_ops(struct gpu_ops *gops)
464{
465 gops->pmu.is_pmu_supported = gp10b_is_pmu_supported;
466 if (gops->privsecurity) {
467 gm20b_init_secure_pmu(gops);
468 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
469 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
470 gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap;
471 gops->pmu.is_priv_load = gp10b_is_priv_load;
472 } else {
473 gk20a_init_pmu_ops(gops);
474 gops->pmu.load_lsfalcon_ucode = NULL;
475 gops->pmu.init_wpr_region = NULL;
476 gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1;
477 }
478 gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg;
479 gops->pmu.lspmuwprinitdone = false;
480 gops->pmu.fecsbootstrapdone = false;
481 gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase;
482 gops->pmu.pmu_elpg_statistics = gp10b_pmu_elpg_statistics;
483 gops->pmu.pmu_pg_init_param = gp10b_pg_gr_init;
484 gops->pmu.pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list;
485 gops->pmu.pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list;
486 gops->pmu.pmu_lpwr_enable_pg = NULL;
487 gops->pmu.pmu_lpwr_disable_pg = NULL;
488 gops->pmu.pmu_pg_param_post_init = NULL;
489 gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd =
490 send_ecc_overide_en_dis_cmd;
491 gops->pmu.reset = gk20a_pmu_reset;
492 gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gp10b;
493}
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-26 08:16:23 -0400