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path: root/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/pmu_gp10b.c17
1 files changed, 11 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
index d6497173..32e7297f 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
@@ -179,11 +179,13 @@ int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
179 u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; 179 u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES;
180 180
181 /* GM20B PMU supports loading FECS and GPCCS only */ 181 /* GM20B PMU supports loading FECS and GPCCS only */
182 if (falconidmask == 0) 182 if (falconidmask == 0) {
183 return -EINVAL; 183 return -EINVAL;
184 }
184 if (falconidmask & ~((1 << LSF_FALCON_ID_FECS) | 185 if (falconidmask & ~((1 << LSF_FALCON_ID_FECS) |
185 (1 << LSF_FALCON_ID_GPCCS))) 186 (1 << LSF_FALCON_ID_GPCCS))) {
186 return -EINVAL; 187 return -EINVAL;
188 }
187 g->pmu_lsf_loaded_falcon_id = 0; 189 g->pmu_lsf_loaded_falcon_id = 0;
188 /* check whether pmu is ready to bootstrap lsf if not wait for it */ 190 /* check whether pmu is ready to bootstrap lsf if not wait for it */
189 if (!g->pmu_lsf_pmu_wpr_init_done) { 191 if (!g->pmu_lsf_pmu_wpr_init_done) {
@@ -201,8 +203,9 @@ int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
201 pmu_wait_message_cond(&g->pmu, 203 pmu_wait_message_cond(&g->pmu,
202 gk20a_get_gr_idle_timeout(g), 204 gk20a_get_gr_idle_timeout(g),
203 &g->pmu_lsf_loaded_falcon_id, falconidmask); 205 &g->pmu_lsf_loaded_falcon_id, falconidmask);
204 if (g->pmu_lsf_loaded_falcon_id != falconidmask) 206 if (g->pmu_lsf_loaded_falcon_id != falconidmask) {
205 return -ETIMEDOUT; 207 return -ETIMEDOUT;
208 }
206 return 0; 209 return 0;
207} 210}
208 211
@@ -247,8 +250,9 @@ int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id)
247 nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, 250 nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
248 pmu_handle_gr_param_msg, pmu, &seq, ~0); 251 pmu_handle_gr_param_msg, pmu, &seq, ~0);
249 252
250 } else 253 } else {
251 return -EINVAL; 254 return -EINVAL;
255 }
252 256
253 return 0; 257 return 0;
254} 258}
@@ -330,8 +334,9 @@ int gp10b_init_pmu_setup_hw1(struct gk20a *g)
330 pwr_fbif_transcfg_target_noncoherent_sysmem_f()); 334 pwr_fbif_transcfg_target_noncoherent_sysmem_f());
331 335
332 err = g->ops.pmu.pmu_nsbootstrap(pmu); 336 err = g->ops.pmu.pmu_nsbootstrap(pmu);
333 if (err) 337 if (err) {
334 return err; 338 return err;
339 }
335 340
336 nvgpu_log_fn(g, "done"); 341 nvgpu_log_fn(g, "done");
337 return 0; 342 return 0;