diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 15b12c74..2d9882c9 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -24,6 +24,8 @@ | |||
24 | #include "pmu_gp10b.h" | 24 | #include "pmu_gp10b.h" |
25 | #include "gp10b_sysfs.h" | 25 | #include "gp10b_sysfs.h" |
26 | 26 | ||
27 | #include <nvgpu/log.h> | ||
28 | |||
27 | #include <nvgpu/hw/gp10b/hw_pwr_gp10b.h> | 29 | #include <nvgpu/hw/gp10b/hw_pwr_gp10b.h> |
28 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | 30 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> |
29 | 31 | ||
@@ -192,8 +194,7 @@ int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) | |||
192 | &g->ops.pmu.lspmuwprinitdone, 1); | 194 | &g->ops.pmu.lspmuwprinitdone, 1); |
193 | /* check again if it still not ready indicate an error */ | 195 | /* check again if it still not ready indicate an error */ |
194 | if (!g->ops.pmu.lspmuwprinitdone) { | 196 | if (!g->ops.pmu.lspmuwprinitdone) { |
195 | gk20a_err(dev_from_gk20a(g), | 197 | nvgpu_err(g, "PMU not ready to load LSF"); |
196 | "PMU not ready to load LSF"); | ||
197 | return -ETIMEDOUT; | 198 | return -ETIMEDOUT; |
198 | } | 199 | } |
199 | } | 200 | } |
@@ -213,7 +214,7 @@ static void pmu_handle_gr_param_msg(struct gk20a *g, struct pmu_msg *msg, | |||
213 | gk20a_dbg_fn(""); | 214 | gk20a_dbg_fn(""); |
214 | 215 | ||
215 | if (status != 0) { | 216 | if (status != 0) { |
216 | gk20a_err(dev_from_gk20a(g), "GR PARAM cmd aborted"); | 217 | nvgpu_err(g, "GR PARAM cmd aborted"); |
217 | /* TBD: disable ELPG */ | 218 | /* TBD: disable ELPG */ |
218 | return; | 219 | return; |
219 | } | 220 | } |
@@ -378,12 +379,12 @@ static void pmu_dump_security_fuses_gp10b(struct gk20a *g) | |||
378 | { | 379 | { |
379 | u32 val; | 380 | u32 val; |
380 | 381 | ||
381 | gk20a_err(dev_from_gk20a(g), "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x", | 382 | nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x", |
382 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); | 383 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); |
383 | gk20a_err(dev_from_gk20a(g), "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", | 384 | nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", |
384 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); | 385 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); |
385 | tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val); | 386 | tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val); |
386 | gk20a_err(dev_from_gk20a(g), "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", | 387 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", |
387 | val); | 388 | val); |
388 | } | 389 | } |
389 | 390 | ||