diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index f40c1b7b..762e2af7 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -365,9 +365,11 @@ static int send_ecc_overide_en_dis_cmd(struct gk20a *g, u32 bitmask) | |||
365 | struct pmu_cmd cmd; | 365 | struct pmu_cmd cmd; |
366 | u32 seq; | 366 | u32 seq; |
367 | int status; | 367 | int status; |
368 | u32 val; | ||
368 | gk20a_dbg_fn(""); | 369 | gk20a_dbg_fn(""); |
369 | 370 | ||
370 | if (!tegra_fuse_readl(FUSE_OPT_ECC_EN)) { | 371 | tegra_fuse_readl(FUSE_OPT_ECC_EN, &val); |
372 | if (!val) { | ||
371 | gk20a_err(dev_from_gk20a(g), "Board not ECC capable"); | 373 | gk20a_err(dev_from_gk20a(g), "Board not ECC capable"); |
372 | return -1; | 374 | return -1; |
373 | } | 375 | } |
@@ -436,12 +438,15 @@ static bool gp10b_is_priv_load(u32 falcon_id) | |||
436 | /*Dump Security related fuses*/ | 438 | /*Dump Security related fuses*/ |
437 | static void pmu_dump_security_fuses_gp10b(struct gk20a *g) | 439 | static void pmu_dump_security_fuses_gp10b(struct gk20a *g) |
438 | { | 440 | { |
441 | u32 val; | ||
442 | |||
439 | gk20a_err(dev_from_gk20a(g), "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x", | 443 | gk20a_err(dev_from_gk20a(g), "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x", |
440 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); | 444 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); |
441 | gk20a_err(dev_from_gk20a(g), "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", | 445 | gk20a_err(dev_from_gk20a(g), "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", |
442 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); | 446 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); |
447 | tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val); | ||
443 | gk20a_err(dev_from_gk20a(g), "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", | 448 | gk20a_err(dev_from_gk20a(g), "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", |
444 | tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0)); | 449 | val); |
445 | } | 450 | } |
446 | 451 | ||
447 | void gp10b_init_pmu_ops(struct gpu_ops *gops) | 452 | void gp10b_init_pmu_ops(struct gpu_ops *gops) |