diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/mm_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 978b6f50..811697c3 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B MMU | 2 | * GP10B MMU |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -53,7 +53,7 @@ int gp10b_init_mm_setup_hw(struct gk20a *g) | |||
53 | struct nvgpu_mem *inst_block = &mm->bar1.inst_block; | 53 | struct nvgpu_mem *inst_block = &mm->bar1.inst_block; |
54 | int err = 0; | 54 | int err = 0; |
55 | 55 | ||
56 | gk20a_dbg_fn(""); | 56 | nvgpu_log_fn(g, " "); |
57 | 57 | ||
58 | g->ops.fb.set_mmu_page_size(g); | 58 | g->ops.fb.set_mmu_page_size(g); |
59 | 59 | ||
@@ -73,7 +73,7 @@ int gp10b_init_mm_setup_hw(struct gk20a *g) | |||
73 | 73 | ||
74 | err = gp10b_replayable_pagefault_buffer_init(g); | 74 | err = gp10b_replayable_pagefault_buffer_init(g); |
75 | 75 | ||
76 | gk20a_dbg_fn("done"); | 76 | nvgpu_log_fn(g, "done"); |
77 | return err; | 77 | return err; |
78 | 78 | ||
79 | } | 79 | } |
@@ -87,7 +87,7 @@ int gp10b_init_bar2_vm(struct gk20a *g) | |||
87 | 87 | ||
88 | /* BAR2 aperture size is 32MB */ | 88 | /* BAR2 aperture size is 32MB */ |
89 | mm->bar2.aperture_size = 32 << 20; | 89 | mm->bar2.aperture_size = 32 << 20; |
90 | gk20a_dbg_info("bar2 vm size = 0x%x", mm->bar2.aperture_size); | 90 | nvgpu_log_info(g, "bar2 vm size = 0x%x", mm->bar2.aperture_size); |
91 | 91 | ||
92 | mm->bar2.vm = nvgpu_vm_init(g, big_page_size, SZ_4K, | 92 | mm->bar2.vm = nvgpu_vm_init(g, big_page_size, SZ_4K, |
93 | mm->bar2.aperture_size - SZ_4K, | 93 | mm->bar2.aperture_size - SZ_4K, |
@@ -115,12 +115,12 @@ int gp10b_init_bar2_mm_hw_setup(struct gk20a *g) | |||
115 | struct nvgpu_mem *inst_block = &mm->bar2.inst_block; | 115 | struct nvgpu_mem *inst_block = &mm->bar2.inst_block; |
116 | u64 inst_pa = nvgpu_inst_block_addr(g, inst_block); | 116 | u64 inst_pa = nvgpu_inst_block_addr(g, inst_block); |
117 | 117 | ||
118 | gk20a_dbg_fn(""); | 118 | nvgpu_log_fn(g, " "); |
119 | 119 | ||
120 | g->ops.fb.set_mmu_page_size(g); | 120 | g->ops.fb.set_mmu_page_size(g); |
121 | 121 | ||
122 | inst_pa = (u32)(inst_pa >> bus_bar2_block_ptr_shift_v()); | 122 | inst_pa = (u32)(inst_pa >> bus_bar2_block_ptr_shift_v()); |
123 | gk20a_dbg_info("bar2 inst block ptr: 0x%08x", (u32)inst_pa); | 123 | nvgpu_log_info(g, "bar2 inst block ptr: 0x%08x", (u32)inst_pa); |
124 | 124 | ||
125 | gk20a_writel(g, bus_bar2_block_r(), | 125 | gk20a_writel(g, bus_bar2_block_r(), |
126 | nvgpu_aperture_mask(g, inst_block, | 126 | nvgpu_aperture_mask(g, inst_block, |
@@ -130,7 +130,7 @@ int gp10b_init_bar2_mm_hw_setup(struct gk20a *g) | |||
130 | bus_bar2_block_mode_virtual_f() | | 130 | bus_bar2_block_mode_virtual_f() | |
131 | bus_bar2_block_ptr_f(inst_pa)); | 131 | bus_bar2_block_ptr_f(inst_pa)); |
132 | 132 | ||
133 | gk20a_dbg_fn("done"); | 133 | nvgpu_log_fn(g, "done"); |
134 | return 0; | 134 | return 0; |
135 | } | 135 | } |
136 | 136 | ||
@@ -433,7 +433,7 @@ void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, | |||
433 | u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); | 433 | u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); |
434 | u32 pdb_addr_hi = u64_hi32(pdb_addr); | 434 | u32 pdb_addr_hi = u64_hi32(pdb_addr); |
435 | 435 | ||
436 | gk20a_dbg_info("pde pa=0x%llx", pdb_addr); | 436 | nvgpu_log_info(g, "pde pa=0x%llx", pdb_addr); |
437 | 437 | ||
438 | nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(), | 438 | nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(), |
439 | nvgpu_aperture_mask(g, vm->pdb.mem, | 439 | nvgpu_aperture_mask(g, vm->pdb.mem, |