diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/mm_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index c25abc78..a183154e 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c | |||
@@ -33,7 +33,6 @@ static int gp10b_init_mm_setup_hw(struct gk20a *g) | |||
33 | { | 33 | { |
34 | struct mm_gk20a *mm = &g->mm; | 34 | struct mm_gk20a *mm = &g->mm; |
35 | struct mem_desc *inst_block = &mm->bar1.inst_block; | 35 | struct mem_desc *inst_block = &mm->bar1.inst_block; |
36 | u64 inst_pa = gk20a_mm_inst_block_addr(g, inst_block); | ||
37 | int err = 0; | 36 | int err = 0; |
38 | 37 | ||
39 | gk20a_dbg_fn(""); | 38 | gk20a_dbg_fn(""); |
@@ -44,7 +43,7 @@ static int gp10b_init_mm_setup_hw(struct gk20a *g) | |||
44 | (g->ops.mm.get_iova_addr(g, g->mm.sysmem_flush.sgt->sgl, 0) | 43 | (g->ops.mm.get_iova_addr(g, g->mm.sysmem_flush.sgt->sgl, 0) |
45 | >> 8ULL)); | 44 | >> 8ULL)); |
46 | 45 | ||
47 | g->ops.mm.bar1_bind(g, inst_pa); | 46 | g->ops.mm.bar1_bind(g, inst_block); |
48 | 47 | ||
49 | if (g->ops.mm.init_bar2_mm_hw_setup) { | 48 | if (g->ops.mm.init_bar2_mm_hw_setup) { |
50 | err = g->ops.mm.init_bar2_mm_hw_setup(g); | 49 | err = g->ops.mm.init_bar2_mm_hw_setup(g); |
@@ -378,21 +377,24 @@ static const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, | |||
378 | return gp10b_mm_levels; | 377 | return gp10b_mm_levels; |
379 | } | 378 | } |
380 | 379 | ||
381 | static void gp10b_mm_init_pdb(struct gk20a *g, struct mem_desc *mem, | 380 | static void gp10b_mm_init_pdb(struct gk20a *g, struct mem_desc *inst_block, |
382 | u64 pdb_addr) | 381 | struct vm_gk20a *vm) |
383 | { | 382 | { |
383 | u64 pdb_addr = g->ops.mm.get_iova_addr(g, vm->pdb.mem.sgt->sgl, 0); | ||
384 | u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); | 384 | u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); |
385 | u32 pdb_addr_hi = u64_hi32(pdb_addr); | 385 | u32 pdb_addr_hi = u64_hi32(pdb_addr); |
386 | 386 | ||
387 | gk20a_mem_wr32(g, mem, ram_in_page_dir_base_lo_w(), | 387 | gk20a_dbg_info("pde pa=0x%llx", pdb_addr); |
388 | (g->mm.vidmem_is_vidmem ? | 388 | |
389 | ram_in_page_dir_base_target_sys_mem_ncoh_f() : | 389 | gk20a_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(), |
390 | gk20a_aperture_mask(g, &vm->pdb.mem, | ||
391 | ram_in_page_dir_base_target_sys_mem_ncoh_f(), | ||
390 | ram_in_page_dir_base_target_vid_mem_f()) | | 392 | ram_in_page_dir_base_target_vid_mem_f()) | |
391 | ram_in_page_dir_base_vol_true_f() | | 393 | ram_in_page_dir_base_vol_true_f() | |
392 | ram_in_page_dir_base_lo_f(pdb_addr_lo) | | 394 | ram_in_page_dir_base_lo_f(pdb_addr_lo) | |
393 | 1 << 10); | 395 | 1 << 10); |
394 | 396 | ||
395 | gk20a_mem_wr32(g, mem, ram_in_page_dir_base_hi_w(), | 397 | gk20a_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(), |
396 | ram_in_page_dir_base_hi_f(pdb_addr_hi)); | 398 | ram_in_page_dir_base_hi_f(pdb_addr_hi)); |
397 | } | 399 | } |
398 | 400 | ||