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path: root/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/mm_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/mm_gp10b.c28
1 files changed, 2 insertions, 26 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
index acd42dd8..50c96f36 100644
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
@@ -34,7 +34,6 @@
34 34
35#include <nvgpu/hw/gp10b/hw_fb_gp10b.h> 35#include <nvgpu/hw/gp10b/hw_fb_gp10b.h>
36#include <nvgpu/hw/gp10b/hw_ram_gp10b.h> 36#include <nvgpu/hw/gp10b/hw_ram_gp10b.h>
37#include <nvgpu/hw/gp10b/hw_bus_gp10b.h>
38#include <nvgpu/hw/gp10b/hw_gmmu_gp10b.h> 37#include <nvgpu/hw/gp10b/hw_gmmu_gp10b.h>
39 38
40u32 gp10b_mm_get_default_big_page_size(void) 39u32 gp10b_mm_get_default_big_page_size(void)
@@ -62,8 +61,8 @@ int gp10b_init_mm_setup_hw(struct gk20a *g)
62 61
63 g->ops.bus.bar1_bind(g, inst_block); 62 g->ops.bus.bar1_bind(g, inst_block);
64 63
65 if (g->ops.mm.init_bar2_mm_hw_setup) { 64 if (g->ops.bus.bar2_bind) {
66 err = g->ops.mm.init_bar2_mm_hw_setup(g); 65 err = g->ops.bus.bar2_bind(g, &g->mm.bar2.inst_block);
67 if (err) 66 if (err)
68 return err; 67 return err;
69 } 68 }
@@ -109,29 +108,6 @@ clean_up_va:
109 return err; 108 return err;
110} 109}
111 110
112int gp10b_init_bar2_mm_hw_setup(struct gk20a *g)
113{
114 struct mm_gk20a *mm = &g->mm;
115 struct nvgpu_mem *inst_block = &mm->bar2.inst_block;
116 u64 inst_pa = nvgpu_inst_block_addr(g, inst_block);
117
118 nvgpu_log_fn(g, " ");
119
120 inst_pa = (u32)(inst_pa >> bus_bar2_block_ptr_shift_v());
121 nvgpu_log_info(g, "bar2 inst block ptr: 0x%08x", (u32)inst_pa);
122
123 gk20a_writel(g, bus_bar2_block_r(),
124 nvgpu_aperture_mask(g, inst_block,
125 bus_bar2_block_target_sys_mem_ncoh_f(),
126 bus_bar2_block_target_sys_mem_coh_f(),
127 bus_bar2_block_target_vid_mem_f()) |
128 bus_bar2_block_mode_virtual_f() |
129 bus_bar2_block_ptr_f(inst_pa));
130
131 nvgpu_log_fn(g, "done");
132 return 0;
133}
134
135static void update_gmmu_pde3_locked(struct vm_gk20a *vm, 111static void update_gmmu_pde3_locked(struct vm_gk20a *vm,
136 const struct gk20a_mmu_level *l, 112 const struct gk20a_mmu_level *l,
137 struct nvgpu_gmmu_pd *pd, 113 struct nvgpu_gmmu_pd *pd,