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path: root/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/mc_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/mc_gp10b.c20
1 files changed, 1 insertions, 19 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
index 39ad8f9b..5a1d5dcc 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
@@ -156,7 +156,7 @@ void mc_gp10b_intr_nonstall_resume(struct gk20a *g)
156 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); 156 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
157} 157}
158 158
159static bool mc_gp10b_is_intr1_pending(struct gk20a *g, 159bool mc_gp10b_is_intr1_pending(struct gk20a *g,
160 enum nvgpu_unit unit, u32 mc_intr_1) 160 enum nvgpu_unit unit, u32 mc_intr_1)
161{ 161{
162 u32 mask = 0; 162 u32 mask = 0;
@@ -179,21 +179,3 @@ static bool mc_gp10b_is_intr1_pending(struct gk20a *g,
179 179
180 return is_pending; 180 return is_pending;
181} 181}
182
183void gp10b_init_mc(struct gpu_ops *gops)
184{
185 gops->mc.intr_enable = mc_gp10b_intr_enable;
186 gops->mc.intr_unit_config = mc_gp10b_intr_unit_config;
187 gops->mc.isr_stall = mc_gp10b_isr_stall;
188 gops->mc.intr_stall = mc_gp10b_intr_stall;
189 gops->mc.intr_stall_pause = mc_gp10b_intr_stall_pause;
190 gops->mc.intr_stall_resume = mc_gp10b_intr_stall_resume;
191 gops->mc.intr_nonstall = mc_gp10b_intr_nonstall;
192 gops->mc.intr_nonstall_pause = mc_gp10b_intr_nonstall_pause;
193 gops->mc.intr_nonstall_resume = mc_gp10b_intr_nonstall_resume;
194 gops->mc.enable = gk20a_mc_enable;
195 gops->mc.disable = gk20a_mc_disable;
196 gops->mc.reset = gk20a_mc_reset;
197 gops->mc.boot_0 = gk20a_mc_boot_0;
198 gops->mc.is_intr1_pending = mc_gp10b_is_intr1_pending;
199}