diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/mc_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 59 |
1 files changed, 47 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 4d9573d1..eda961b6 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP20B master | 2 | * GP20B master |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -101,6 +101,9 @@ irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g) | |||
101 | irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | 101 | irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) |
102 | { | 102 | { |
103 | u32 mc_intr_0; | 103 | u32 mc_intr_0; |
104 | u32 engine_id_idx; | ||
105 | u32 active_engine_id = 0; | ||
106 | u32 engine_enum = ENGINE_INVAL_GK20A; | ||
104 | 107 | ||
105 | gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); | 108 | gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); |
106 | 109 | ||
@@ -108,11 +111,26 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | |||
108 | 111 | ||
109 | gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); | 112 | gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); |
110 | 113 | ||
111 | if (mc_intr_0 & g->fifo.engine_info[ENGINE_GR_GK20A].intr_mask) | 114 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { |
112 | gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); | 115 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; |
113 | if (mc_intr_0 & g->fifo.engine_info[ENGINE_CE2_GK20A].intr_mask | 116 | |
114 | && g->ops.ce2.isr_stall) | 117 | if (mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) { |
115 | g->ops.ce2.isr_stall(g); | 118 | engine_enum = g->fifo.engine_info[active_engine_id].engine_enum; |
119 | /* GR Engine */ | ||
120 | if (engine_enum == ENGINE_GR_GK20A) { | ||
121 | gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); | ||
122 | } | ||
123 | |||
124 | /* CE Engine */ | ||
125 | if (((engine_enum == ENGINE_GRCE_GK20A) || | ||
126 | (engine_enum == ENGINE_ASYNC_CE_GK20A)) && | ||
127 | g->ops.ce2.isr_stall){ | ||
128 | g->ops.ce2.isr_stall(g, | ||
129 | g->fifo.engine_info[active_engine_id].inst_id, | ||
130 | g->fifo.engine_info[active_engine_id].pri_base); | ||
131 | } | ||
132 | } | ||
133 | } | ||
116 | if (mc_intr_0 & mc_intr_pfifo_pending_f()) | 134 | if (mc_intr_0 & mc_intr_pfifo_pending_f()) |
117 | gk20a_fifo_isr(g); | 135 | gk20a_fifo_isr(g); |
118 | if (mc_intr_0 & mc_intr_pmu_pending_f()) | 136 | if (mc_intr_0 & mc_intr_pmu_pending_f()) |
@@ -133,6 +151,9 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | |||
133 | irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) | 151 | irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) |
134 | { | 152 | { |
135 | u32 mc_intr_1; | 153 | u32 mc_intr_1; |
154 | u32 engine_id_idx; | ||
155 | u32 active_engine_id = 0; | ||
156 | u32 engine_enum = ENGINE_INVAL_GK20A; | ||
136 | 157 | ||
137 | gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); | 158 | gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); |
138 | 159 | ||
@@ -142,13 +163,27 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) | |||
142 | 163 | ||
143 | if (mc_intr_1 & mc_intr_pfifo_pending_f()) | 164 | if (mc_intr_1 & mc_intr_pfifo_pending_f()) |
144 | gk20a_fifo_nonstall_isr(g); | 165 | gk20a_fifo_nonstall_isr(g); |
145 | if (mc_intr_1 & g->fifo.engine_info[ENGINE_GR_GK20A].intr_mask) | ||
146 | gk20a_gr_nonstall_isr(g); | ||
147 | if (mc_intr_1 & g->fifo.engine_info[ENGINE_CE2_GK20A].intr_mask | ||
148 | && g->ops.ce2.isr_nonstall) | ||
149 | g->ops.ce2.isr_nonstall(g); | ||
150 | |||
151 | 166 | ||
167 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { | ||
168 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; | ||
169 | |||
170 | if (mc_intr_1 & g->fifo.engine_info[active_engine_id].intr_mask) { | ||
171 | engine_enum = g->fifo.engine_info[active_engine_id].engine_enum; | ||
172 | /* GR Engine */ | ||
173 | if (engine_enum == ENGINE_GR_GK20A) { | ||
174 | gk20a_gr_nonstall_isr(g); | ||
175 | } | ||
176 | |||
177 | /* CE Engine */ | ||
178 | if (((engine_enum == ENGINE_GRCE_GK20A) || | ||
179 | (engine_enum == ENGINE_ASYNC_CE_GK20A)) && | ||
180 | g->ops.ce2.isr_nonstall) { | ||
181 | g->ops.ce2.isr_nonstall(g, | ||
182 | g->fifo.engine_info[active_engine_id].inst_id, | ||
183 | g->fifo.engine_info[active_engine_id].pri_base); | ||
184 | } | ||
185 | } | ||
186 | } | ||
152 | 187 | ||
153 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), | 188 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), |
154 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); | 189 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); |