1 files changed, 20 insertions, 29 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
index 4a48d7fa..bfc7a3d4 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
@@ -1,7 +1,7 @@
 /*
- * GP20B master
+ * GP10B master
  *
- * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -67,25 +67,6 @@ void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
         gk20a_writel(g, reg, mask);
 }
 
-irqreturn_t mc_gp10b_isr_stall(struct gk20a *g)
-{
-        u32 mc_intr_0;
-
-        if (!g->power_on)
-                return IRQ_NONE;
-
-        /* not from gpu when sharing irq with others */
-        mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
-        if (unlikely(!mc_intr_0))
-                return IRQ_NONE;
-
-        gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff);
-
-        atomic_inc(&g->hw_irq_stall_count);
-
-        return IRQ_WAKE_THREAD;
-}
-
 irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g)
 {
         u32 mc_intr_1;
@@ -117,7 +98,7 @@ irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g)
         return IRQ_HANDLED;
 }
 
-irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
+void mc_gp10b_isr_stall(struct gk20a *g)
 {
         u32 mc_intr_0;
         int hw_irq_count;
@@ -126,8 +107,6 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
         u32 active_engine_id = 0;
         u32 engine_enum = ENGINE_INVAL_GK20A;
 
-        gk20a_dbg(gpu_dbg_intr, "interrupt thread launched");
-
         mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
         hw_irq_count = atomic_read(&g->hw_irq_stall_count);
 
@@ -172,12 +151,22 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
 
         gk20a_dbg(gpu_dbg_intr, "stall intr done 0x%08x\n", mc_intr_0);
 
-        gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
-                        g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
+}
 
-        wake_up_all(&g->sw_irq_stall_last_handled_wq);
+u32 mc_gp10b_intr_stall(struct gk20a *g)
+{
+        return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
+}
 
-        return IRQ_HANDLED;
+void mc_gp10b_intr_stall_pause(struct gk20a *g)
+{
+        gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), 0xffffffff);
+}
+
+void mc_gp10b_intr_stall_resume(struct gk20a *g)
+{
+        gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
+                        g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
 }
 
 void gp10b_init_mc(struct gpu_ops *gops)
@@ -185,8 +174,10 @@ void gp10b_init_mc(struct gpu_ops *gops)
         gops->mc.intr_enable = mc_gp10b_intr_enable;
         gops->mc.intr_unit_config = mc_gp10b_intr_unit_config;
         gops->mc.isr_stall = mc_gp10b_isr_stall;
+        gops->mc.intr_stall = mc_gp10b_intr_stall;
+        gops->mc.intr_stall_pause = mc_gp10b_intr_stall_pause;
+        gops->mc.intr_stall_resume = mc_gp10b_intr_stall_resume;
         gops->mc.isr_nonstall = mc_gp10b_isr_nonstall;
-        gops->mc.isr_thread_stall = mc_gp10b_intr_thread_stall;
         gops->mc.isr_thread_nonstall = mc_gk20a_intr_thread_nonstall;
         gops->mc.isr_nonstall_cb = mc_gk20a_nonstall_cb;
         gops->mc.enable = gk20a_mc_enable;