1 files changed, 8 insertions, 8 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
index 5a1d5dcc..718869f6 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
@@ -29,7 +29,7 @@ void mc_gp10b_intr_enable(struct gk20a *g)
 
         gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
                                 0xffffffff);
-        g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] =
+        g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
                                 mc_intr_pfifo_pending_f() |
                                  mc_intr_priv_ring_pending_f() |
                                  mc_intr_pbus_pending_f() |
@@ -37,15 +37,15 @@ void mc_gp10b_intr_enable(struct gk20a *g)
                                  mc_intr_replayable_fault_pending_f() |
                                  eng_intr_mask;
         gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
-                        g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
+                        g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
 
         gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
                                 0xffffffff);
-        g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
+        g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
                                 mc_intr_pfifo_pending_f() |
                                  eng_intr_mask;
         gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
-                        g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
+                        g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
 }
 
 void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
@@ -58,11 +58,11 @@ void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
                         NVGPU_MC_INTR_NONSTALLING);
         if (enable) {
                 reg = mc_intr_en_set_r(intr_index);
-                g->ops.mc.intr_mask_restore[intr_index] |= mask;
+                g->mc_intr_mask_restore[intr_index] |= mask;
 
         } else {
                 reg = mc_intr_en_clear_r(intr_index);
-                g->ops.mc.intr_mask_restore[intr_index] &= ~mask;
+                g->mc_intr_mask_restore[intr_index] &= ~mask;
         }
 
         gk20a_writel(g, reg, mask);
@@ -136,7 +136,7 @@ void mc_gp10b_intr_stall_pause(struct gk20a *g)
 void mc_gp10b_intr_stall_resume(struct gk20a *g)
 {
         gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
-                        g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
+                        g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
 }
 
 u32 mc_gp10b_intr_nonstall(struct gk20a *g)
@@ -153,7 +153,7 @@ void mc_gp10b_intr_nonstall_pause(struct gk20a *g)
 void mc_gp10b_intr_nonstall_resume(struct gk20a *g)
 {
         gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
-                        g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
+                        g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
 }
 
 bool mc_gp10b_is_intr1_pending(struct gk20a *g,