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path: root/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/ltc_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/ltc_gp10b.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
index d52a10ad..d6634b14 100644
--- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
@@ -61,7 +61,7 @@ int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
61 /* max memory size (MB) to cover */ 61 /* max memory size (MB) to cover */
62 u32 max_size = gr->max_comptag_mem; 62 u32 max_size = gr->max_comptag_mem;
63 /* one tag line covers 64KB */ 63 /* one tag line covers 64KB */
64 u32 max_comptag_lines = max_size << 4; 64 u32 max_comptag_lines = max_size << 4U;
65 65
66 u32 hw_max_comptag_lines = 66 u32 hw_max_comptag_lines =
67 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(); 67 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v();
@@ -71,7 +71,7 @@ int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
71 u32 comptags_per_cacheline = 71 u32 comptags_per_cacheline =
72 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(cbc_param); 72 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(cbc_param);
73 u32 cacheline_size = 73 u32 cacheline_size =
74 512 << ltc_ltcs_ltss_cbc_param_cache_line_size_v(cbc_param); 74 512U << ltc_ltcs_ltss_cbc_param_cache_line_size_v(cbc_param);
75 u32 slices_per_ltc = 75 u32 slices_per_ltc =
76 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(cbc_param); 76 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(cbc_param);
77 u32 cbc_param2 = 77 u32 cbc_param2 =
@@ -85,7 +85,7 @@ int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
85 85
86 gk20a_dbg_fn(""); 86 gk20a_dbg_fn("");
87 87
88 if (max_comptag_lines == 0) 88 if (max_comptag_lines == 0U)
89 return 0; 89 return 0;
90 90
91 /* Already initialized */ 91 /* Already initialized */
@@ -138,18 +138,18 @@ int gp10b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op,
138 struct gr_gk20a *gr = &g->gr; 138 struct gr_gk20a *gr = &g->gr;
139 struct nvgpu_timeout timeout; 139 struct nvgpu_timeout timeout;
140 int err = 0; 140 int err = 0;
141 u32 ltc, slice, ctrl1, val, hw_op = 0; 141 u32 ltc, slice, ctrl1, val, hw_op = 0U;
142 u32 slices_per_ltc = ltc_ltcs_ltss_cbc_param_slices_per_ltc_v( 142 u32 slices_per_ltc = ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(
143 gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r())); 143 gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r()));
144 u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE); 144 u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
145 u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); 145 u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
146 const u32 max_lines = 16384; 146 const u32 max_lines = 16384U;
147 147
148 nvgpu_log_fn(g, " "); 148 nvgpu_log_fn(g, " ");
149 149
150 trace_gk20a_ltc_cbc_ctrl_start(g->name, op, min, max); 150 trace_gk20a_ltc_cbc_ctrl_start(g->name, op, min, max);
151 151
152 if (gr->compbit_store.mem.size == 0) 152 if (gr->compbit_store.mem.size == 0U)
153 return 0; 153 return 0;
154 154
155 while (1) { 155 while (1) {
@@ -235,7 +235,7 @@ void gp10b_ltc_isr(struct gk20a *g)
235 mc_intr = gk20a_readl(g, mc_intr_ltc_r()); 235 mc_intr = gk20a_readl(g, mc_intr_ltc_r());
236 nvgpu_err(g, "mc_ltc_intr: %08x", mc_intr); 236 nvgpu_err(g, "mc_ltc_intr: %08x", mc_intr);
237 for (ltc = 0; ltc < g->ltc_count; ltc++) { 237 for (ltc = 0; ltc < g->ltc_count; ltc++) {
238 if ((mc_intr & 1 << ltc) == 0) 238 if ((mc_intr & 1U << ltc) == 0)
239 continue; 239 continue;
240 for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { 240 for (slice = 0; slice < g->gr.slices_per_ltc; slice++) {
241 u32 offset = ltc_stride * ltc + lts_stride * slice; 241 u32 offset = ltc_stride * ltc + lts_stride * slice;