diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/ltc_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index b0938f75..1e5807d5 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | |||
@@ -156,14 +156,16 @@ int gp10b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, | |||
156 | nvgpu_log_info(g, "clearing CBC lines %u..%u", min, iter_max); | 156 | nvgpu_log_info(g, "clearing CBC lines %u..%u", min, iter_max); |
157 | 157 | ||
158 | if (op == gk20a_cbc_op_clear) { | 158 | if (op == gk20a_cbc_op_clear) { |
159 | gk20a_writel( | 159 | nvgpu_writel_check( |
160 | g, ltc_ltcs_ltss_cbc_ctrl2_r(), | 160 | g, ltc_ltcs_ltss_cbc_ctrl2_r(), |
161 | ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f( | 161 | ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f( |
162 | min)); | 162 | min)); |
163 | gk20a_writel( | 163 | |
164 | nvgpu_writel_check( | ||
164 | g, ltc_ltcs_ltss_cbc_ctrl3_r(), | 165 | g, ltc_ltcs_ltss_cbc_ctrl3_r(), |
165 | ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f( | 166 | ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f( |
166 | iter_max)); | 167 | iter_max)); |
168 | |||
167 | hw_op = ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(); | 169 | hw_op = ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(); |
168 | full_cache_op = false; | 170 | full_cache_op = false; |
169 | } else if (op == gk20a_cbc_op_clean) { | 171 | } else if (op == gk20a_cbc_op_clean) { |
@@ -251,10 +253,9 @@ void gp10b_ltc_isr(struct gk20a *g) | |||
251 | ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val); | 253 | ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val); |
252 | ecc_stats_reg_val &= | 254 | ecc_stats_reg_val &= |
253 | ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m()); | 255 | ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m()); |
254 | gk20a_writel(g, | 256 | nvgpu_writel_check(g, |
255 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset, | 257 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset, |
256 | ecc_stats_reg_val); | 258 | ecc_stats_reg_val); |
257 | |||
258 | g->ops.mm.l2_flush(g, true); | 259 | g->ops.mm.l2_flush(g, true); |
259 | } | 260 | } |
260 | if (ltc_intr & | 261 | if (ltc_intr & |
@@ -271,16 +272,16 @@ void gp10b_ltc_isr(struct gk20a *g) | |||
271 | ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val); | 272 | ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val); |
272 | ecc_stats_reg_val &= | 273 | ecc_stats_reg_val &= |
273 | ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m()); | 274 | ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m()); |
274 | gk20a_writel(g, | 275 | nvgpu_writel_check(g, |
275 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset, | 276 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset, |
276 | ecc_stats_reg_val); | 277 | ecc_stats_reg_val); |
277 | } | 278 | } |
278 | 279 | ||
279 | nvgpu_err(g, "ltc%d, slice %d: %08x", | 280 | nvgpu_err(g, "ltc%d, slice %d: %08x", |
280 | ltc, slice, ltc_intr); | 281 | ltc, slice, ltc_intr); |
281 | gk20a_writel(g, ltc_ltc0_lts0_intr_r() + | 282 | nvgpu_writel_check(g, ltc_ltc0_lts0_intr_r() + |
282 | ltc_stride * ltc + lts_stride * slice, | 283 | ltc_stride * ltc + lts_stride * slice, |
283 | ltc_intr); | 284 | ltc_intr); |
284 | } | 285 | } |
285 | } | 286 | } |
286 | } | 287 | } |
@@ -314,5 +315,5 @@ void gp10b_ltc_set_enabled(struct gk20a *g, bool enabled) | |||
314 | /* bypass enabled (no caching) */ | 315 | /* bypass enabled (no caching) */ |
315 | reg |= reg_f; | 316 | reg |= reg_f; |
316 | 317 | ||
317 | gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); | 318 | nvgpu_writel_check(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); |
318 | } | 319 | } |