diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/ltc_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 225 |
1 files changed, 225 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c new file mode 100644 index 00000000..31c79aff --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | |||
@@ -0,0 +1,225 @@ | |||
1 | /* | ||
2 | * GP10B L2 | ||
3 | * | ||
4 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #include <linux/types.h> | ||
17 | |||
18 | #include <dt-bindings/memory/tegra-swgroup.h> | ||
19 | |||
20 | #include "gk20a/gk20a.h" | ||
21 | #include "gm20b/ltc_gm20b.h" | ||
22 | #include "hw_mc_gp10b.h" | ||
23 | #include "hw_ltc_gp10b.h" | ||
24 | |||
25 | #include "gk20a/ltc_common.c" | ||
26 | |||
27 | static int gp10b_determine_L2_size_bytes(struct gk20a *g) | ||
28 | { | ||
29 | u32 tmp; | ||
30 | int ret; | ||
31 | |||
32 | gk20a_dbg_fn(""); | ||
33 | |||
34 | tmp = gk20a_readl(g, ltc_ltc0_lts0_tstg_info_1_r()); | ||
35 | |||
36 | ret = g->ltc_count * | ||
37 | ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(tmp)*1024 * | ||
38 | ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(tmp); | ||
39 | |||
40 | gk20a_dbg(gpu_dbg_info, "L2 size: %d\n", ret); | ||
41 | |||
42 | gk20a_dbg_fn("done"); | ||
43 | |||
44 | return ret; | ||
45 | } | ||
46 | |||
47 | static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | ||
48 | { | ||
49 | /* max memory size (MB) to cover */ | ||
50 | u32 max_size = gr->max_comptag_mem; | ||
51 | /* one tag line covers 64KB */ | ||
52 | u32 max_comptag_lines = max_size << 4; | ||
53 | |||
54 | u32 hw_max_comptag_lines = | ||
55 | ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(); | ||
56 | |||
57 | u32 cbc_param = | ||
58 | gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r()); | ||
59 | u32 comptags_per_cacheline = | ||
60 | ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(cbc_param); | ||
61 | u32 cacheline_size = | ||
62 | 512 << ltc_ltcs_ltss_cbc_param_cache_line_size_v(cbc_param); | ||
63 | u32 slices_per_ltc = | ||
64 | ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(cbc_param); | ||
65 | u32 cbc_param2 = | ||
66 | gk20a_readl(g, ltc_ltcs_ltss_cbc_param2_r()); | ||
67 | u32 gobs_per_comptagline_per_slice = | ||
68 | ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(cbc_param2); | ||
69 | |||
70 | u32 compbit_backing_size; | ||
71 | |||
72 | int err; | ||
73 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
74 | |||
75 | gk20a_dbg_fn(""); | ||
76 | |||
77 | if (max_comptag_lines == 0) | ||
78 | return 0; | ||
79 | |||
80 | if (max_comptag_lines > hw_max_comptag_lines) | ||
81 | max_comptag_lines = hw_max_comptag_lines; | ||
82 | |||
83 | compbit_backing_size = | ||
84 | roundup(max_comptag_lines * gobs_per_comptagline_per_slice, | ||
85 | cacheline_size); | ||
86 | compbit_backing_size = | ||
87 | roundup(compbit_backing_size * slices_per_ltc * g->ltc_count, | ||
88 | g->ops.fb.compressible_page_size(g)); | ||
89 | |||
90 | /* aligned to 2KB * ltc_count */ | ||
91 | compbit_backing_size += | ||
92 | g->ltc_count << ltc_ltcs_ltss_cbc_base_alignment_shift_v(); | ||
93 | |||
94 | /* must be a multiple of 64KB */ | ||
95 | compbit_backing_size = roundup(compbit_backing_size, 64*1024); | ||
96 | |||
97 | gk20a_dbg_info("compbit backing store size : %d", | ||
98 | compbit_backing_size); | ||
99 | gk20a_dbg_info("max comptag lines : %d", | ||
100 | max_comptag_lines); | ||
101 | gk20a_dbg_info("gobs_per_comptagline_per_slice: %d", | ||
102 | gobs_per_comptagline_per_slice); | ||
103 | |||
104 | if (platform->is_fmodel) | ||
105 | err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); | ||
106 | else | ||
107 | err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); | ||
108 | |||
109 | if (err) | ||
110 | return err; | ||
111 | |||
112 | err = gk20a_comptag_allocator_init(&gr->comp_tags, max_comptag_lines); | ||
113 | if (err) | ||
114 | return err; | ||
115 | |||
116 | gr->comptags_per_cacheline = comptags_per_cacheline; | ||
117 | gr->slices_per_ltc = slices_per_ltc; | ||
118 | gr->cacheline_size = cacheline_size; | ||
119 | gr->gobs_per_comptagline_per_slice = gobs_per_comptagline_per_slice; | ||
120 | |||
121 | return 0; | ||
122 | } | ||
123 | |||
124 | static void gp10b_ltc_isr(struct gk20a *g) | ||
125 | { | ||
126 | u32 mc_intr, ltc_intr; | ||
127 | unsigned int ltc, slice; | ||
128 | u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE); | ||
129 | u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); | ||
130 | |||
131 | mc_intr = gk20a_readl(g, mc_intr_ltc_r()); | ||
132 | gk20a_err(dev_from_gk20a(g), "mc_ltc_intr: %08x", | ||
133 | mc_intr); | ||
134 | for (ltc = 0; ltc < g->ltc_count; ltc++) { | ||
135 | if ((mc_intr & 1 << ltc) == 0) | ||
136 | continue; | ||
137 | for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { | ||
138 | u32 offset = ltc_stride * ltc + lts_stride * slice; | ||
139 | ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + offset); | ||
140 | |||
141 | /* Detect and handle ECC errors */ | ||
142 | if (ltc_intr & | ||
143 | ltc_ltcs_ltss_intr_ecc_sec_error_pending_f()) { | ||
144 | u32 ecc_stats_reg_val; | ||
145 | |||
146 | gk20a_err(dev_from_gk20a(g), | ||
147 | "Single bit error detected in GPU L2!"); | ||
148 | |||
149 | ecc_stats_reg_val = | ||
150 | gk20a_readl(g, | ||
151 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset); | ||
152 | g->gr.t18x.ecc_stats.l2_sec_count.counters[ltc] += | ||
153 | ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val); | ||
154 | ecc_stats_reg_val &= | ||
155 | ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m()); | ||
156 | gk20a_writel(g, | ||
157 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset, | ||
158 | ecc_stats_reg_val); | ||
159 | |||
160 | g->ops.mm.l2_flush(g, true); | ||
161 | } | ||
162 | if (ltc_intr & | ||
163 | ltc_ltcs_ltss_intr_ecc_ded_error_pending_f()) { | ||
164 | u32 ecc_stats_reg_val; | ||
165 | |||
166 | gk20a_err(dev_from_gk20a(g), | ||
167 | "Double bit error detected in GPU L2!"); | ||
168 | |||
169 | ecc_stats_reg_val = | ||
170 | gk20a_readl(g, | ||
171 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset); | ||
172 | g->gr.t18x.ecc_stats.l2_ded_count.counters[ltc] += | ||
173 | ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val); | ||
174 | ecc_stats_reg_val &= | ||
175 | ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m()); | ||
176 | gk20a_writel(g, | ||
177 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset, | ||
178 | ecc_stats_reg_val); | ||
179 | } | ||
180 | |||
181 | gk20a_err(dev_from_gk20a(g), "ltc%d, slice %d: %08x", | ||
182 | ltc, slice, ltc_intr); | ||
183 | gk20a_writel(g, ltc_ltc0_lts0_intr_r() + | ||
184 | ltc_stride * ltc + lts_stride * slice, | ||
185 | ltc_intr); | ||
186 | } | ||
187 | } | ||
188 | } | ||
189 | |||
190 | static void gp10b_ltc_init_fs_state(struct gk20a *g) | ||
191 | { | ||
192 | u32 ltc_intr; | ||
193 | |||
194 | gm20b_ltc_init_fs_state(g); | ||
195 | |||
196 | gk20a_writel(g, ltc_ltca_g_axi_pctrl_r(), | ||
197 | ltc_ltca_g_axi_pctrl_user_sid_f(TEGRA_SID_GPUB)); | ||
198 | |||
199 | /* Enable ECC interrupts */ | ||
200 | ltc_intr = gk20a_readl(g, ltc_ltcs_ltss_intr_r()); | ||
201 | ltc_intr |= ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() | | ||
202 | ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(); | ||
203 | gk20a_writel(g, ltc_ltcs_ltss_intr_r(), | ||
204 | ltc_intr); | ||
205 | } | ||
206 | |||
207 | void gp10b_init_ltc(struct gpu_ops *gops) | ||
208 | { | ||
209 | gops->ltc.determine_L2_size_bytes = gp10b_determine_L2_size_bytes; | ||
210 | gops->ltc.set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry; | ||
211 | gops->ltc.set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry; | ||
212 | gops->ltc.init_cbc = gk20a_ltc_init_cbc; | ||
213 | |||
214 | /* GM20b specific ops. */ | ||
215 | gops->ltc.init_fs_state = gp10b_ltc_init_fs_state; | ||
216 | gops->ltc.init_comptags = gp10b_ltc_init_comptags; | ||
217 | gops->ltc.cbc_ctrl = gm20b_ltc_cbc_ctrl; | ||
218 | gops->ltc.elpg_flush = gm20b_ltc_g_elpg_flush_locked; | ||
219 | gops->ltc.isr = gp10b_ltc_isr; | ||
220 | gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config; | ||
221 | gops->ltc.flush = gm20b_flush_ltc; | ||
222 | #ifdef CONFIG_DEBUG_FS | ||
223 | gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs; | ||
224 | #endif | ||
225 | } | ||