diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h | 825 |
1 files changed, 825 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h new file mode 100644 index 00000000..9a3591c7 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h | |||
@@ -0,0 +1,825 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_pwr_gp10b_h_ | ||
51 | #define _hw_pwr_gp10b_h_ | ||
52 | |||
53 | static inline u32 pwr_falcon_irqsset_r(void) | ||
54 | { | ||
55 | return 0x0010a000; | ||
56 | } | ||
57 | static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) | ||
58 | { | ||
59 | return 0x40; | ||
60 | } | ||
61 | static inline u32 pwr_falcon_irqsclr_r(void) | ||
62 | { | ||
63 | return 0x0010a004; | ||
64 | } | ||
65 | static inline u32 pwr_falcon_irqstat_r(void) | ||
66 | { | ||
67 | return 0x0010a008; | ||
68 | } | ||
69 | static inline u32 pwr_falcon_irqstat_halt_true_f(void) | ||
70 | { | ||
71 | return 0x10; | ||
72 | } | ||
73 | static inline u32 pwr_falcon_irqstat_exterr_true_f(void) | ||
74 | { | ||
75 | return 0x20; | ||
76 | } | ||
77 | static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) | ||
78 | { | ||
79 | return 0x40; | ||
80 | } | ||
81 | static inline u32 pwr_falcon_irqmode_r(void) | ||
82 | { | ||
83 | return 0x0010a00c; | ||
84 | } | ||
85 | static inline u32 pwr_falcon_irqmset_r(void) | ||
86 | { | ||
87 | return 0x0010a010; | ||
88 | } | ||
89 | static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) | ||
90 | { | ||
91 | return (v & 0x1) << 0; | ||
92 | } | ||
93 | static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) | ||
94 | { | ||
95 | return (v & 0x1) << 1; | ||
96 | } | ||
97 | static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) | ||
98 | { | ||
99 | return (v & 0x1) << 2; | ||
100 | } | ||
101 | static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) | ||
102 | { | ||
103 | return (v & 0x1) << 3; | ||
104 | } | ||
105 | static inline u32 pwr_falcon_irqmset_halt_f(u32 v) | ||
106 | { | ||
107 | return (v & 0x1) << 4; | ||
108 | } | ||
109 | static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) | ||
110 | { | ||
111 | return (v & 0x1) << 5; | ||
112 | } | ||
113 | static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) | ||
114 | { | ||
115 | return (v & 0x1) << 6; | ||
116 | } | ||
117 | static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) | ||
118 | { | ||
119 | return (v & 0x1) << 7; | ||
120 | } | ||
121 | static inline u32 pwr_falcon_irqmclr_r(void) | ||
122 | { | ||
123 | return 0x0010a014; | ||
124 | } | ||
125 | static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) | ||
126 | { | ||
127 | return (v & 0x1) << 0; | ||
128 | } | ||
129 | static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) | ||
130 | { | ||
131 | return (v & 0x1) << 1; | ||
132 | } | ||
133 | static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) | ||
134 | { | ||
135 | return (v & 0x1) << 2; | ||
136 | } | ||
137 | static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) | ||
138 | { | ||
139 | return (v & 0x1) << 3; | ||
140 | } | ||
141 | static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) | ||
142 | { | ||
143 | return (v & 0x1) << 4; | ||
144 | } | ||
145 | static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) | ||
146 | { | ||
147 | return (v & 0x1) << 5; | ||
148 | } | ||
149 | static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) | ||
150 | { | ||
151 | return (v & 0x1) << 6; | ||
152 | } | ||
153 | static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) | ||
154 | { | ||
155 | return (v & 0x1) << 7; | ||
156 | } | ||
157 | static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) | ||
158 | { | ||
159 | return (v & 0xff) << 8; | ||
160 | } | ||
161 | static inline u32 pwr_falcon_irqmask_r(void) | ||
162 | { | ||
163 | return 0x0010a018; | ||
164 | } | ||
165 | static inline u32 pwr_falcon_irqdest_r(void) | ||
166 | { | ||
167 | return 0x0010a01c; | ||
168 | } | ||
169 | static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) | ||
170 | { | ||
171 | return (v & 0x1) << 0; | ||
172 | } | ||
173 | static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) | ||
174 | { | ||
175 | return (v & 0x1) << 1; | ||
176 | } | ||
177 | static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) | ||
178 | { | ||
179 | return (v & 0x1) << 2; | ||
180 | } | ||
181 | static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) | ||
182 | { | ||
183 | return (v & 0x1) << 3; | ||
184 | } | ||
185 | static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) | ||
186 | { | ||
187 | return (v & 0x1) << 4; | ||
188 | } | ||
189 | static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) | ||
190 | { | ||
191 | return (v & 0x1) << 5; | ||
192 | } | ||
193 | static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) | ||
194 | { | ||
195 | return (v & 0x1) << 6; | ||
196 | } | ||
197 | static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) | ||
198 | { | ||
199 | return (v & 0x1) << 7; | ||
200 | } | ||
201 | static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) | ||
202 | { | ||
203 | return (v & 0xff) << 8; | ||
204 | } | ||
205 | static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) | ||
206 | { | ||
207 | return (v & 0x1) << 16; | ||
208 | } | ||
209 | static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) | ||
210 | { | ||
211 | return (v & 0x1) << 17; | ||
212 | } | ||
213 | static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) | ||
214 | { | ||
215 | return (v & 0x1) << 18; | ||
216 | } | ||
217 | static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) | ||
218 | { | ||
219 | return (v & 0x1) << 19; | ||
220 | } | ||
221 | static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) | ||
222 | { | ||
223 | return (v & 0x1) << 20; | ||
224 | } | ||
225 | static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) | ||
226 | { | ||
227 | return (v & 0x1) << 21; | ||
228 | } | ||
229 | static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) | ||
230 | { | ||
231 | return (v & 0x1) << 22; | ||
232 | } | ||
233 | static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) | ||
234 | { | ||
235 | return (v & 0x1) << 23; | ||
236 | } | ||
237 | static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) | ||
238 | { | ||
239 | return (v & 0xff) << 24; | ||
240 | } | ||
241 | static inline u32 pwr_falcon_curctx_r(void) | ||
242 | { | ||
243 | return 0x0010a050; | ||
244 | } | ||
245 | static inline u32 pwr_falcon_nxtctx_r(void) | ||
246 | { | ||
247 | return 0x0010a054; | ||
248 | } | ||
249 | static inline u32 pwr_falcon_mailbox0_r(void) | ||
250 | { | ||
251 | return 0x0010a040; | ||
252 | } | ||
253 | static inline u32 pwr_falcon_mailbox1_r(void) | ||
254 | { | ||
255 | return 0x0010a044; | ||
256 | } | ||
257 | static inline u32 pwr_falcon_itfen_r(void) | ||
258 | { | ||
259 | return 0x0010a048; | ||
260 | } | ||
261 | static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) | ||
262 | { | ||
263 | return 0x1; | ||
264 | } | ||
265 | static inline u32 pwr_falcon_idlestate_r(void) | ||
266 | { | ||
267 | return 0x0010a04c; | ||
268 | } | ||
269 | static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) | ||
270 | { | ||
271 | return (r >> 0) & 0x1; | ||
272 | } | ||
273 | static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) | ||
274 | { | ||
275 | return (r >> 1) & 0x7fff; | ||
276 | } | ||
277 | static inline u32 pwr_falcon_os_r(void) | ||
278 | { | ||
279 | return 0x0010a080; | ||
280 | } | ||
281 | static inline u32 pwr_falcon_engctl_r(void) | ||
282 | { | ||
283 | return 0x0010a0a4; | ||
284 | } | ||
285 | static inline u32 pwr_falcon_cpuctl_r(void) | ||
286 | { | ||
287 | return 0x0010a100; | ||
288 | } | ||
289 | static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) | ||
290 | { | ||
291 | return (v & 0x1) << 1; | ||
292 | } | ||
293 | static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) | ||
294 | { | ||
295 | return (v & 0x1) << 4; | ||
296 | } | ||
297 | static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) | ||
298 | { | ||
299 | return 0x1 << 4; | ||
300 | } | ||
301 | static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) | ||
302 | { | ||
303 | return (r >> 4) & 0x1; | ||
304 | } | ||
305 | static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) | ||
306 | { | ||
307 | return (v & 0x1) << 6; | ||
308 | } | ||
309 | static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) | ||
310 | { | ||
311 | return 0x1 << 6; | ||
312 | } | ||
313 | static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) | ||
314 | { | ||
315 | return (r >> 6) & 0x1; | ||
316 | } | ||
317 | static inline u32 pwr_falcon_cpuctl_alias_r(void) | ||
318 | { | ||
319 | return 0x0010a130; | ||
320 | } | ||
321 | static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) | ||
322 | { | ||
323 | return (v & 0x1) << 1; | ||
324 | } | ||
325 | static inline u32 pwr_pmu_scpctl_stat_r(void) | ||
326 | { | ||
327 | return 0x0010ac08; | ||
328 | } | ||
329 | static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) | ||
330 | { | ||
331 | return (v & 0x1) << 20; | ||
332 | } | ||
333 | static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) | ||
334 | { | ||
335 | return 0x1 << 20; | ||
336 | } | ||
337 | static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) | ||
338 | { | ||
339 | return (r >> 20) & 0x1; | ||
340 | } | ||
341 | static inline u32 pwr_falcon_imemc_r(u32 i) | ||
342 | { | ||
343 | return 0x0010a180 + i*16; | ||
344 | } | ||
345 | static inline u32 pwr_falcon_imemc_offs_f(u32 v) | ||
346 | { | ||
347 | return (v & 0x3f) << 2; | ||
348 | } | ||
349 | static inline u32 pwr_falcon_imemc_blk_f(u32 v) | ||
350 | { | ||
351 | return (v & 0xff) << 8; | ||
352 | } | ||
353 | static inline u32 pwr_falcon_imemc_aincw_f(u32 v) | ||
354 | { | ||
355 | return (v & 0x1) << 24; | ||
356 | } | ||
357 | static inline u32 pwr_falcon_imemd_r(u32 i) | ||
358 | { | ||
359 | return 0x0010a184 + i*16; | ||
360 | } | ||
361 | static inline u32 pwr_falcon_imemt_r(u32 i) | ||
362 | { | ||
363 | return 0x0010a188 + i*16; | ||
364 | } | ||
365 | static inline u32 pwr_falcon_sctl_r(void) | ||
366 | { | ||
367 | return 0x0010a240; | ||
368 | } | ||
369 | static inline u32 pwr_falcon_mmu_phys_sec_r(void) | ||
370 | { | ||
371 | return 0x00100ce4; | ||
372 | } | ||
373 | static inline u32 pwr_falcon_bootvec_r(void) | ||
374 | { | ||
375 | return 0x0010a104; | ||
376 | } | ||
377 | static inline u32 pwr_falcon_bootvec_vec_f(u32 v) | ||
378 | { | ||
379 | return (v & 0xffffffff) << 0; | ||
380 | } | ||
381 | static inline u32 pwr_falcon_dmactl_r(void) | ||
382 | { | ||
383 | return 0x0010a10c; | ||
384 | } | ||
385 | static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) | ||
386 | { | ||
387 | return 0x1 << 1; | ||
388 | } | ||
389 | static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) | ||
390 | { | ||
391 | return 0x1 << 2; | ||
392 | } | ||
393 | static inline u32 pwr_falcon_hwcfg_r(void) | ||
394 | { | ||
395 | return 0x0010a108; | ||
396 | } | ||
397 | static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) | ||
398 | { | ||
399 | return (r >> 0) & 0x1ff; | ||
400 | } | ||
401 | static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) | ||
402 | { | ||
403 | return (r >> 9) & 0x1ff; | ||
404 | } | ||
405 | static inline u32 pwr_falcon_dmatrfbase_r(void) | ||
406 | { | ||
407 | return 0x0010a110; | ||
408 | } | ||
409 | static inline u32 pwr_falcon_dmatrfbase1_r(void) | ||
410 | { | ||
411 | return 0x0010a128; | ||
412 | } | ||
413 | static inline u32 pwr_falcon_dmatrfmoffs_r(void) | ||
414 | { | ||
415 | return 0x0010a114; | ||
416 | } | ||
417 | static inline u32 pwr_falcon_dmatrfcmd_r(void) | ||
418 | { | ||
419 | return 0x0010a118; | ||
420 | } | ||
421 | static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) | ||
422 | { | ||
423 | return (v & 0x1) << 4; | ||
424 | } | ||
425 | static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) | ||
426 | { | ||
427 | return (v & 0x1) << 5; | ||
428 | } | ||
429 | static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) | ||
430 | { | ||
431 | return (v & 0x7) << 8; | ||
432 | } | ||
433 | static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) | ||
434 | { | ||
435 | return (v & 0x7) << 12; | ||
436 | } | ||
437 | static inline u32 pwr_falcon_dmatrffboffs_r(void) | ||
438 | { | ||
439 | return 0x0010a11c; | ||
440 | } | ||
441 | static inline u32 pwr_falcon_exterraddr_r(void) | ||
442 | { | ||
443 | return 0x0010a168; | ||
444 | } | ||
445 | static inline u32 pwr_falcon_exterrstat_r(void) | ||
446 | { | ||
447 | return 0x0010a16c; | ||
448 | } | ||
449 | static inline u32 pwr_falcon_exterrstat_valid_m(void) | ||
450 | { | ||
451 | return 0x1 << 31; | ||
452 | } | ||
453 | static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) | ||
454 | { | ||
455 | return (r >> 31) & 0x1; | ||
456 | } | ||
457 | static inline u32 pwr_falcon_exterrstat_valid_true_v(void) | ||
458 | { | ||
459 | return 0x00000001; | ||
460 | } | ||
461 | static inline u32 pwr_pmu_falcon_icd_cmd_r(void) | ||
462 | { | ||
463 | return 0x0010a200; | ||
464 | } | ||
465 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) | ||
466 | { | ||
467 | return 4; | ||
468 | } | ||
469 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) | ||
470 | { | ||
471 | return (v & 0xf) << 0; | ||
472 | } | ||
473 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) | ||
474 | { | ||
475 | return 0xf << 0; | ||
476 | } | ||
477 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) | ||
478 | { | ||
479 | return (r >> 0) & 0xf; | ||
480 | } | ||
481 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) | ||
482 | { | ||
483 | return 0x8; | ||
484 | } | ||
485 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) | ||
486 | { | ||
487 | return 0xe; | ||
488 | } | ||
489 | static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) | ||
490 | { | ||
491 | return (v & 0x1f) << 8; | ||
492 | } | ||
493 | static inline u32 pwr_pmu_falcon_icd_rdata_r(void) | ||
494 | { | ||
495 | return 0x0010a20c; | ||
496 | } | ||
497 | static inline u32 pwr_falcon_dmemc_r(u32 i) | ||
498 | { | ||
499 | return 0x0010a1c0 + i*8; | ||
500 | } | ||
501 | static inline u32 pwr_falcon_dmemc_offs_f(u32 v) | ||
502 | { | ||
503 | return (v & 0x3f) << 2; | ||
504 | } | ||
505 | static inline u32 pwr_falcon_dmemc_offs_m(void) | ||
506 | { | ||
507 | return 0x3f << 2; | ||
508 | } | ||
509 | static inline u32 pwr_falcon_dmemc_blk_f(u32 v) | ||
510 | { | ||
511 | return (v & 0xff) << 8; | ||
512 | } | ||
513 | static inline u32 pwr_falcon_dmemc_blk_m(void) | ||
514 | { | ||
515 | return 0xff << 8; | ||
516 | } | ||
517 | static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) | ||
518 | { | ||
519 | return (v & 0x1) << 24; | ||
520 | } | ||
521 | static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) | ||
522 | { | ||
523 | return (v & 0x1) << 25; | ||
524 | } | ||
525 | static inline u32 pwr_falcon_dmemd_r(u32 i) | ||
526 | { | ||
527 | return 0x0010a1c4 + i*8; | ||
528 | } | ||
529 | static inline u32 pwr_pmu_new_instblk_r(void) | ||
530 | { | ||
531 | return 0x0010a480; | ||
532 | } | ||
533 | static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) | ||
534 | { | ||
535 | return (v & 0xfffffff) << 0; | ||
536 | } | ||
537 | static inline u32 pwr_pmu_new_instblk_target_fb_f(void) | ||
538 | { | ||
539 | return 0x0; | ||
540 | } | ||
541 | static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) | ||
542 | { | ||
543 | return 0x20000000; | ||
544 | } | ||
545 | static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) | ||
546 | { | ||
547 | return 0x30000000; | ||
548 | } | ||
549 | static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) | ||
550 | { | ||
551 | return (v & 0x1) << 30; | ||
552 | } | ||
553 | static inline u32 pwr_pmu_mutex_id_r(void) | ||
554 | { | ||
555 | return 0x0010a488; | ||
556 | } | ||
557 | static inline u32 pwr_pmu_mutex_id_value_v(u32 r) | ||
558 | { | ||
559 | return (r >> 0) & 0xff; | ||
560 | } | ||
561 | static inline u32 pwr_pmu_mutex_id_value_init_v(void) | ||
562 | { | ||
563 | return 0x00000000; | ||
564 | } | ||
565 | static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) | ||
566 | { | ||
567 | return 0x000000ff; | ||
568 | } | ||
569 | static inline u32 pwr_pmu_mutex_id_release_r(void) | ||
570 | { | ||
571 | return 0x0010a48c; | ||
572 | } | ||
573 | static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) | ||
574 | { | ||
575 | return (v & 0xff) << 0; | ||
576 | } | ||
577 | static inline u32 pwr_pmu_mutex_id_release_value_m(void) | ||
578 | { | ||
579 | return 0xff << 0; | ||
580 | } | ||
581 | static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) | ||
582 | { | ||
583 | return 0x00000000; | ||
584 | } | ||
585 | static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) | ||
586 | { | ||
587 | return 0x0; | ||
588 | } | ||
589 | static inline u32 pwr_pmu_mutex_r(u32 i) | ||
590 | { | ||
591 | return 0x0010a580 + i*4; | ||
592 | } | ||
593 | static inline u32 pwr_pmu_mutex__size_1_v(void) | ||
594 | { | ||
595 | return 0x00000010; | ||
596 | } | ||
597 | static inline u32 pwr_pmu_mutex_value_f(u32 v) | ||
598 | { | ||
599 | return (v & 0xff) << 0; | ||
600 | } | ||
601 | static inline u32 pwr_pmu_mutex_value_v(u32 r) | ||
602 | { | ||
603 | return (r >> 0) & 0xff; | ||
604 | } | ||
605 | static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) | ||
606 | { | ||
607 | return 0x0; | ||
608 | } | ||
609 | static inline u32 pwr_pmu_queue_head_r(u32 i) | ||
610 | { | ||
611 | return 0x0010a4a0 + i*4; | ||
612 | } | ||
613 | static inline u32 pwr_pmu_queue_head__size_1_v(void) | ||
614 | { | ||
615 | return 0x00000004; | ||
616 | } | ||
617 | static inline u32 pwr_pmu_queue_head_address_f(u32 v) | ||
618 | { | ||
619 | return (v & 0xffffffff) << 0; | ||
620 | } | ||
621 | static inline u32 pwr_pmu_queue_head_address_v(u32 r) | ||
622 | { | ||
623 | return (r >> 0) & 0xffffffff; | ||
624 | } | ||
625 | static inline u32 pwr_pmu_queue_tail_r(u32 i) | ||
626 | { | ||
627 | return 0x0010a4b0 + i*4; | ||
628 | } | ||
629 | static inline u32 pwr_pmu_queue_tail__size_1_v(void) | ||
630 | { | ||
631 | return 0x00000004; | ||
632 | } | ||
633 | static inline u32 pwr_pmu_queue_tail_address_f(u32 v) | ||
634 | { | ||
635 | return (v & 0xffffffff) << 0; | ||
636 | } | ||
637 | static inline u32 pwr_pmu_queue_tail_address_v(u32 r) | ||
638 | { | ||
639 | return (r >> 0) & 0xffffffff; | ||
640 | } | ||
641 | static inline u32 pwr_pmu_msgq_head_r(void) | ||
642 | { | ||
643 | return 0x0010a4c8; | ||
644 | } | ||
645 | static inline u32 pwr_pmu_msgq_head_val_f(u32 v) | ||
646 | { | ||
647 | return (v & 0xffffffff) << 0; | ||
648 | } | ||
649 | static inline u32 pwr_pmu_msgq_head_val_v(u32 r) | ||
650 | { | ||
651 | return (r >> 0) & 0xffffffff; | ||
652 | } | ||
653 | static inline u32 pwr_pmu_msgq_tail_r(void) | ||
654 | { | ||
655 | return 0x0010a4cc; | ||
656 | } | ||
657 | static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) | ||
658 | { | ||
659 | return (v & 0xffffffff) << 0; | ||
660 | } | ||
661 | static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) | ||
662 | { | ||
663 | return (r >> 0) & 0xffffffff; | ||
664 | } | ||
665 | static inline u32 pwr_pmu_idle_mask_r(u32 i) | ||
666 | { | ||
667 | return 0x0010a504 + i*16; | ||
668 | } | ||
669 | static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) | ||
670 | { | ||
671 | return 0x1; | ||
672 | } | ||
673 | static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) | ||
674 | { | ||
675 | return 0x200000; | ||
676 | } | ||
677 | static inline u32 pwr_pmu_idle_count_r(u32 i) | ||
678 | { | ||
679 | return 0x0010a508 + i*16; | ||
680 | } | ||
681 | static inline u32 pwr_pmu_idle_count_value_f(u32 v) | ||
682 | { | ||
683 | return (v & 0x7fffffff) << 0; | ||
684 | } | ||
685 | static inline u32 pwr_pmu_idle_count_value_v(u32 r) | ||
686 | { | ||
687 | return (r >> 0) & 0x7fffffff; | ||
688 | } | ||
689 | static inline u32 pwr_pmu_idle_count_reset_f(u32 v) | ||
690 | { | ||
691 | return (v & 0x1) << 31; | ||
692 | } | ||
693 | static inline u32 pwr_pmu_idle_ctrl_r(u32 i) | ||
694 | { | ||
695 | return 0x0010a50c + i*16; | ||
696 | } | ||
697 | static inline u32 pwr_pmu_idle_ctrl_value_m(void) | ||
698 | { | ||
699 | return 0x3 << 0; | ||
700 | } | ||
701 | static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) | ||
702 | { | ||
703 | return 0x2; | ||
704 | } | ||
705 | static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) | ||
706 | { | ||
707 | return 0x3; | ||
708 | } | ||
709 | static inline u32 pwr_pmu_idle_ctrl_filter_m(void) | ||
710 | { | ||
711 | return 0x1 << 2; | ||
712 | } | ||
713 | static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) | ||
714 | { | ||
715 | return 0x0; | ||
716 | } | ||
717 | static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) | ||
718 | { | ||
719 | return 0x0010a9f0 + i*8; | ||
720 | } | ||
721 | static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) | ||
722 | { | ||
723 | return 0x0010a9f4 + i*8; | ||
724 | } | ||
725 | static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) | ||
726 | { | ||
727 | return 0x0010aa30 + i*8; | ||
728 | } | ||
729 | static inline u32 pwr_pmu_debug_r(u32 i) | ||
730 | { | ||
731 | return 0x0010a5c0 + i*4; | ||
732 | } | ||
733 | static inline u32 pwr_pmu_debug__size_1_v(void) | ||
734 | { | ||
735 | return 0x00000004; | ||
736 | } | ||
737 | static inline u32 pwr_pmu_mailbox_r(u32 i) | ||
738 | { | ||
739 | return 0x0010a450 + i*4; | ||
740 | } | ||
741 | static inline u32 pwr_pmu_mailbox__size_1_v(void) | ||
742 | { | ||
743 | return 0x0000000c; | ||
744 | } | ||
745 | static inline u32 pwr_pmu_bar0_addr_r(void) | ||
746 | { | ||
747 | return 0x0010a7a0; | ||
748 | } | ||
749 | static inline u32 pwr_pmu_bar0_data_r(void) | ||
750 | { | ||
751 | return 0x0010a7a4; | ||
752 | } | ||
753 | static inline u32 pwr_pmu_bar0_ctl_r(void) | ||
754 | { | ||
755 | return 0x0010a7ac; | ||
756 | } | ||
757 | static inline u32 pwr_pmu_bar0_timeout_r(void) | ||
758 | { | ||
759 | return 0x0010a7a8; | ||
760 | } | ||
761 | static inline u32 pwr_pmu_bar0_fecs_error_r(void) | ||
762 | { | ||
763 | return 0x0010a988; | ||
764 | } | ||
765 | static inline u32 pwr_pmu_bar0_error_status_r(void) | ||
766 | { | ||
767 | return 0x0010a7b0; | ||
768 | } | ||
769 | static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) | ||
770 | { | ||
771 | return 0x0010a6c0 + i*4; | ||
772 | } | ||
773 | static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) | ||
774 | { | ||
775 | return 0x0010a6e8 + i*4; | ||
776 | } | ||
777 | static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) | ||
778 | { | ||
779 | return 0x0010a710 + i*4; | ||
780 | } | ||
781 | static inline u32 pwr_pmu_pg_intren_r(u32 i) | ||
782 | { | ||
783 | return 0x0010a760 + i*4; | ||
784 | } | ||
785 | static inline u32 pwr_fbif_transcfg_r(u32 i) | ||
786 | { | ||
787 | return 0x0010ae00 + i*4; | ||
788 | } | ||
789 | static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) | ||
790 | { | ||
791 | return 0x0; | ||
792 | } | ||
793 | static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) | ||
794 | { | ||
795 | return 0x1; | ||
796 | } | ||
797 | static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) | ||
798 | { | ||
799 | return 0x2; | ||
800 | } | ||
801 | static inline u32 pwr_fbif_transcfg_mem_type_s(void) | ||
802 | { | ||
803 | return 1; | ||
804 | } | ||
805 | static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) | ||
806 | { | ||
807 | return (v & 0x1) << 2; | ||
808 | } | ||
809 | static inline u32 pwr_fbif_transcfg_mem_type_m(void) | ||
810 | { | ||
811 | return 0x1 << 2; | ||
812 | } | ||
813 | static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) | ||
814 | { | ||
815 | return (r >> 2) & 0x1; | ||
816 | } | ||
817 | static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) | ||
818 | { | ||
819 | return 0x0; | ||
820 | } | ||
821 | static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) | ||
822 | { | ||
823 | return 0x4; | ||
824 | } | ||
825 | #endif | ||