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Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c748
1 files changed, 748 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
new file mode 100644
index 00000000..9b3d1a2c
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -0,0 +1,748 @@
1/*
2 * GP10B Tegra HAL interface
3 *
4 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include "gk20a/gk20a.h"
26#include "gk20a/fifo_gk20a.h"
27#include "gk20a/fecs_trace_gk20a.h"
28#include "gk20a/mm_gk20a.h"
29#include "gk20a/dbg_gpu_gk20a.h"
30#include "gk20a/css_gr_gk20a.h"
31#include "gk20a/bus_gk20a.h"
32#include "gk20a/pramin_gk20a.h"
33#include "gk20a/flcn_gk20a.h"
34#include "gk20a/regops_gk20a.h"
35#include "gk20a/mc_gk20a.h"
36#include "gk20a/fb_gk20a.h"
37#include "gk20a/pmu_gk20a.h"
38#include "gk20a/gr_gk20a.h"
39#include "gk20a/tsg_gk20a.h"
40
41#include "gp10b/gr_gp10b.h"
42#include "gp10b/fecs_trace_gp10b.h"
43#include "gp10b/mc_gp10b.h"
44#include "gp10b/ltc_gp10b.h"
45#include "gp10b/mm_gp10b.h"
46#include "gp10b/ce_gp10b.h"
47#include "gp10b/fb_gp10b.h"
48#include "gp10b/pmu_gp10b.h"
49#include "gp10b/gr_ctx_gp10b.h"
50#include "gp10b/fifo_gp10b.h"
51#include "gp10b/gp10b_gating_reglist.h"
52#include "gp10b/regops_gp10b.h"
53#include "gp10b/therm_gp10b.h"
54#include "gp10b/priv_ring_gp10b.h"
55
56#include "gm20b/ltc_gm20b.h"
57#include "gm20b/gr_gm20b.h"
58#include "gm20b/fifo_gm20b.h"
59#include "gm20b/acr_gm20b.h"
60#include "gm20b/pmu_gm20b.h"
61#include "gm20b/clk_gm20b.h"
62#include "gm20b/fb_gm20b.h"
63#include "gm20b/mm_gm20b.h"
64
65#include "gp10b.h"
66#include "hal_gp10b.h"
67
68#include <nvgpu/debug.h>
69#include <nvgpu/bug.h>
70#include <nvgpu/enabled.h>
71#include <nvgpu/bus.h>
72#include <nvgpu/ctxsw_trace.h>
73
74#include <nvgpu/hw/gp10b/hw_proj_gp10b.h>
75#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
76#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
77#include <nvgpu/hw/gp10b/hw_ram_gp10b.h>
78#include <nvgpu/hw/gp10b/hw_top_gp10b.h>
79#include <nvgpu/hw/gp10b/hw_pram_gp10b.h>
80#include <nvgpu/hw/gp10b/hw_pwr_gp10b.h>
81
82int gp10b_get_litter_value(struct gk20a *g, int value)
83{
84 int ret = EINVAL;
85 switch (value) {
86 case GPU_LIT_NUM_GPCS:
87 ret = proj_scal_litter_num_gpcs_v();
88 break;
89 case GPU_LIT_NUM_PES_PER_GPC:
90 ret = proj_scal_litter_num_pes_per_gpc_v();
91 break;
92 case GPU_LIT_NUM_ZCULL_BANKS:
93 ret = proj_scal_litter_num_zcull_banks_v();
94 break;
95 case GPU_LIT_NUM_TPC_PER_GPC:
96 ret = proj_scal_litter_num_tpc_per_gpc_v();
97 break;
98 case GPU_LIT_NUM_SM_PER_TPC:
99 ret = proj_scal_litter_num_sm_per_tpc_v();
100 break;
101 case GPU_LIT_NUM_FBPS:
102 ret = proj_scal_litter_num_fbps_v();
103 break;
104 case GPU_LIT_GPC_BASE:
105 ret = proj_gpc_base_v();
106 break;
107 case GPU_LIT_GPC_STRIDE:
108 ret = proj_gpc_stride_v();
109 break;
110 case GPU_LIT_GPC_SHARED_BASE:
111 ret = proj_gpc_shared_base_v();
112 break;
113 case GPU_LIT_TPC_IN_GPC_BASE:
114 ret = proj_tpc_in_gpc_base_v();
115 break;
116 case GPU_LIT_TPC_IN_GPC_STRIDE:
117 ret = proj_tpc_in_gpc_stride_v();
118 break;
119 case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
120 ret = proj_tpc_in_gpc_shared_base_v();
121 break;
122 case GPU_LIT_PPC_IN_GPC_BASE:
123 ret = proj_ppc_in_gpc_base_v();
124 break;
125 case GPU_LIT_PPC_IN_GPC_STRIDE:
126 ret = proj_ppc_in_gpc_stride_v();
127 break;
128 case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
129 ret = proj_ppc_in_gpc_shared_base_v();
130 break;
131 case GPU_LIT_ROP_BASE:
132 ret = proj_rop_base_v();
133 break;
134 case GPU_LIT_ROP_STRIDE:
135 ret = proj_rop_stride_v();
136 break;
137 case GPU_LIT_ROP_SHARED_BASE:
138 ret = proj_rop_shared_base_v();
139 break;
140 case GPU_LIT_HOST_NUM_ENGINES:
141 ret = proj_host_num_engines_v();
142 break;
143 case GPU_LIT_HOST_NUM_PBDMA:
144 ret = proj_host_num_pbdma_v();
145 break;
146 case GPU_LIT_LTC_STRIDE:
147 ret = proj_ltc_stride_v();
148 break;
149 case GPU_LIT_LTS_STRIDE:
150 ret = proj_lts_stride_v();
151 break;
152 /* Even though GP10B doesn't have an FBPA unit, the HW reports one,
153 * and the microcode as a result leaves space in the context buffer
154 * for one, so make sure SW accounts for this also.
155 */
156 case GPU_LIT_NUM_FBPAS:
157 ret = proj_scal_litter_num_fbpas_v();
158 break;
159 /* Hardcode FBPA values other than NUM_FBPAS to 0. */
160 case GPU_LIT_FBPA_STRIDE:
161 case GPU_LIT_FBPA_BASE:
162 case GPU_LIT_FBPA_SHARED_BASE:
163 ret = 0;
164 break;
165 case GPU_LIT_TWOD_CLASS:
166 ret = FERMI_TWOD_A;
167 break;
168 case GPU_LIT_THREED_CLASS:
169 ret = PASCAL_A;
170 break;
171 case GPU_LIT_COMPUTE_CLASS:
172 ret = PASCAL_COMPUTE_A;
173 break;
174 case GPU_LIT_GPFIFO_CLASS:
175 ret = PASCAL_CHANNEL_GPFIFO_A;
176 break;
177 case GPU_LIT_I2M_CLASS:
178 ret = KEPLER_INLINE_TO_MEMORY_B;
179 break;
180 case GPU_LIT_DMA_COPY_CLASS:
181 ret = PASCAL_DMA_COPY_A;
182 break;
183
184 default:
185 nvgpu_err(g, "Missing definition %d", value);
186 BUG();
187 break;
188 }
189
190 return ret;
191}
192
193static const struct gpu_ops gp10b_ops = {
194 .ltc = {
195 .determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
196 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
197 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
198 .init_cbc = gm20b_ltc_init_cbc,
199 .init_fs_state = gp10b_ltc_init_fs_state,
200 .init_comptags = gp10b_ltc_init_comptags,
201 .cbc_ctrl = gm20b_ltc_cbc_ctrl,
202 .isr = gp10b_ltc_isr,
203 .cbc_fix_config = gm20b_ltc_cbc_fix_config,
204 .flush = gm20b_flush_ltc,
205 .set_enabled = gp10b_ltc_set_enabled,
206 },
207 .ce2 = {
208 .isr_stall = gp10b_ce_isr,
209 .isr_nonstall = gp10b_ce_nonstall_isr,
210 },
211 .gr = {
212 .get_patch_slots = gr_gk20a_get_patch_slots,
213 .init_gpc_mmu = gr_gm20b_init_gpc_mmu,
214 .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults,
215 .cb_size_default = gr_gp10b_cb_size_default,
216 .calc_global_ctx_buffer_size =
217 gr_gp10b_calc_global_ctx_buffer_size,
218 .commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb,
219 .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb,
220 .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager,
221 .commit_global_pagepool = gr_gp10b_commit_global_pagepool,
222 .handle_sw_method = gr_gp10b_handle_sw_method,
223 .set_alpha_circular_buffer_size =
224 gr_gp10b_set_alpha_circular_buffer_size,
225 .set_circular_buffer_size = gr_gp10b_set_circular_buffer_size,
226 .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions,
227 .is_valid_class = gr_gp10b_is_valid_class,
228 .is_valid_gfx_class = gr_gp10b_is_valid_gfx_class,
229 .is_valid_compute_class = gr_gp10b_is_valid_compute_class,
230 .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
231 .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
232 .init_fs_state = gr_gp10b_init_fs_state,
233 .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
234 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
235 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
236 .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask,
237 .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask,
238 .free_channel_ctx = gk20a_free_channel_ctx,
239 .alloc_obj_ctx = gk20a_alloc_obj_ctx,
240 .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull,
241 .get_zcull_info = gr_gk20a_get_zcull_info,
242 .is_tpc_addr = gr_gm20b_is_tpc_addr,
243 .get_tpc_num = gr_gm20b_get_tpc_num,
244 .detect_sm_arch = gr_gm20b_detect_sm_arch,
245 .add_zbc_color = gr_gp10b_add_zbc_color,
246 .add_zbc_depth = gr_gp10b_add_zbc_depth,
247 .zbc_set_table = gk20a_gr_zbc_set_table,
248 .zbc_query_table = gr_gk20a_query_zbc,
249 .pmu_save_zbc = gk20a_pmu_save_zbc,
250 .add_zbc = gr_gk20a_add_zbc,
251 .pagepool_default_size = gr_gp10b_pagepool_default_size,
252 .init_ctx_state = gr_gp10b_init_ctx_state,
253 .alloc_gr_ctx = gr_gp10b_alloc_gr_ctx,
254 .free_gr_ctx = gr_gp10b_free_gr_ctx,
255 .update_ctxsw_preemption_mode =
256 gr_gp10b_update_ctxsw_preemption_mode,
257 .dump_gr_regs = gr_gp10b_dump_gr_status_regs,
258 .update_pc_sampling = gr_gm20b_update_pc_sampling,
259 .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask,
260 .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp,
261 .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc,
262 .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask,
263 .get_max_fbps_count = gr_gm20b_get_max_fbps_count,
264 .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info,
265 .wait_empty = gr_gp10b_wait_empty,
266 .init_cyclestats = gr_gm20b_init_cyclestats,
267 .set_sm_debug_mode = gr_gk20a_set_sm_debug_mode,
268 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
269 .bpt_reg_info = gr_gm20b_bpt_reg_info,
270 .get_access_map = gr_gp10b_get_access_map,
271 .handle_fecs_error = gr_gp10b_handle_fecs_error,
272 .handle_sm_exception = gr_gp10b_handle_sm_exception,
273 .handle_tex_exception = gr_gp10b_handle_tex_exception,
274 .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions,
275 .enable_exceptions = gk20a_gr_enable_exceptions,
276 .get_lrf_tex_ltc_dram_override = get_ecc_override_val,
277 .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode,
278 .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode,
279 .record_sm_error_state = gm20b_gr_record_sm_error_state,
280 .update_sm_error_state = gm20b_gr_update_sm_error_state,
281 .clear_sm_error_state = gm20b_gr_clear_sm_error_state,
282 .suspend_contexts = gr_gp10b_suspend_contexts,
283 .resume_contexts = gr_gk20a_resume_contexts,
284 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
285 .init_sm_id_table = gr_gk20a_init_sm_id_table,
286 .load_smid_config = gr_gp10b_load_smid_config,
287 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
288 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
289 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
290 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
291 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
292 .setup_rop_mapping = gr_gk20a_setup_rop_mapping,
293 .program_zcull_mapping = gr_gk20a_program_zcull_mapping,
294 .commit_global_timeslice = gr_gk20a_commit_global_timeslice,
295 .commit_inst = gr_gk20a_commit_inst,
296 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
297 .write_pm_ptr = gr_gk20a_write_pm_ptr,
298 .init_elcg_mode = gr_gk20a_init_elcg_mode,
299 .load_tpc_mask = gr_gm20b_load_tpc_mask,
300 .inval_icache = gr_gk20a_inval_icache,
301 .trigger_suspend = gr_gk20a_trigger_suspend,
302 .wait_for_pause = gr_gk20a_wait_for_pause,
303 .resume_from_pause = gr_gk20a_resume_from_pause,
304 .clear_sm_errors = gr_gk20a_clear_sm_errors,
305 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
306 .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel,
307 .sm_debugger_attached = gk20a_gr_sm_debugger_attached,
308 .suspend_single_sm = gk20a_gr_suspend_single_sm,
309 .suspend_all_sms = gk20a_gr_suspend_all_sms,
310 .resume_single_sm = gk20a_gr_resume_single_sm,
311 .resume_all_sms = gk20a_gr_resume_all_sms,
312 .get_sm_hww_warp_esr = gp10b_gr_get_sm_hww_warp_esr,
313 .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr,
314 .get_sm_no_lock_down_hww_global_esr_mask =
315 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask,
316 .lock_down_sm = gk20a_gr_lock_down_sm,
317 .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down,
318 .clear_sm_hww = gm20b_gr_clear_sm_hww,
319 .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf,
320 .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs,
321 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
322 .set_boosted_ctx = gr_gp10b_set_boosted_ctx,
323 .set_preemption_mode = gr_gp10b_set_preemption_mode,
324 .set_czf_bypass = gr_gp10b_set_czf_bypass,
325 .init_czf_bypass = gr_gp10b_init_czf_bypass,
326 .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception,
327 .set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va,
328 .init_preemption_state = gr_gp10b_init_preemption_state,
329 .update_boosted_ctx = gr_gp10b_update_boosted_ctx,
330 .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
331 .create_gr_sysfs = gr_gp10b_create_sysfs,
332 .set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode,
333 .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data,
334 },
335 .fb = {
336 .reset = fb_gk20a_reset,
337 .init_hw = gk20a_fb_init_hw,
338 .init_fs_state = fb_gm20b_init_fs_state,
339 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
340 .set_use_full_comp_tag_line =
341 gm20b_fb_set_use_full_comp_tag_line,
342 .compression_page_size = gp10b_fb_compression_page_size,
343 .compressible_page_size = gp10b_fb_compressible_page_size,
344 .vpr_info_fetch = gm20b_fb_vpr_info_fetch,
345 .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
346 .read_wpr_info = gm20b_fb_read_wpr_info,
347 .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
348 .set_debug_mode = gm20b_fb_set_debug_mode,
349 .tlb_invalidate = gk20a_fb_tlb_invalidate,
350 .mem_unlock = NULL,
351 },
352 .clock_gating = {
353 .slcg_bus_load_gating_prod =
354 gp10b_slcg_bus_load_gating_prod,
355 .slcg_ce2_load_gating_prod =
356 gp10b_slcg_ce2_load_gating_prod,
357 .slcg_chiplet_load_gating_prod =
358 gp10b_slcg_chiplet_load_gating_prod,
359 .slcg_ctxsw_firmware_load_gating_prod =
360 gp10b_slcg_ctxsw_firmware_load_gating_prod,
361 .slcg_fb_load_gating_prod =
362 gp10b_slcg_fb_load_gating_prod,
363 .slcg_fifo_load_gating_prod =
364 gp10b_slcg_fifo_load_gating_prod,
365 .slcg_gr_load_gating_prod =
366 gr_gp10b_slcg_gr_load_gating_prod,
367 .slcg_ltc_load_gating_prod =
368 ltc_gp10b_slcg_ltc_load_gating_prod,
369 .slcg_perf_load_gating_prod =
370 gp10b_slcg_perf_load_gating_prod,
371 .slcg_priring_load_gating_prod =
372 gp10b_slcg_priring_load_gating_prod,
373 .slcg_pmu_load_gating_prod =
374 gp10b_slcg_pmu_load_gating_prod,
375 .slcg_therm_load_gating_prod =
376 gp10b_slcg_therm_load_gating_prod,
377 .slcg_xbar_load_gating_prod =
378 gp10b_slcg_xbar_load_gating_prod,
379 .blcg_bus_load_gating_prod =
380 gp10b_blcg_bus_load_gating_prod,
381 .blcg_ce_load_gating_prod =
382 gp10b_blcg_ce_load_gating_prod,
383 .blcg_ctxsw_firmware_load_gating_prod =
384 gp10b_blcg_ctxsw_firmware_load_gating_prod,
385 .blcg_fb_load_gating_prod =
386 gp10b_blcg_fb_load_gating_prod,
387 .blcg_fifo_load_gating_prod =
388 gp10b_blcg_fifo_load_gating_prod,
389 .blcg_gr_load_gating_prod =
390 gp10b_blcg_gr_load_gating_prod,
391 .blcg_ltc_load_gating_prod =
392 gp10b_blcg_ltc_load_gating_prod,
393 .blcg_pwr_csb_load_gating_prod =
394 gp10b_blcg_pwr_csb_load_gating_prod,
395 .blcg_pmu_load_gating_prod =
396 gp10b_blcg_pmu_load_gating_prod,
397 .blcg_xbar_load_gating_prod =
398 gp10b_blcg_xbar_load_gating_prod,
399 .pg_gr_load_gating_prod =
400 gr_gp10b_pg_gr_load_gating_prod,
401 },
402 .fifo = {
403 .init_fifo_setup_hw = gk20a_init_fifo_setup_hw,
404 .bind_channel = channel_gm20b_bind,
405 .unbind_channel = gk20a_fifo_channel_unbind,
406 .disable_channel = gk20a_fifo_disable_channel,
407 .enable_channel = gk20a_fifo_enable_channel,
408 .alloc_inst = gk20a_fifo_alloc_inst,
409 .free_inst = gk20a_fifo_free_inst,
410 .setup_ramfc = channel_gp10b_setup_ramfc,
411 .channel_set_timeslice = gk20a_fifo_set_timeslice,
412 .default_timeslice_us = gk20a_fifo_default_timeslice_us,
413 .setup_userd = gk20a_fifo_setup_userd,
414 .userd_gp_get = gk20a_fifo_userd_gp_get,
415 .userd_gp_put = gk20a_fifo_userd_gp_put,
416 .userd_pb_get = gk20a_fifo_userd_pb_get,
417 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
418 .preempt_channel = gk20a_fifo_preempt_channel,
419 .preempt_tsg = gk20a_fifo_preempt_tsg,
420 .enable_tsg = gk20a_enable_tsg,
421 .disable_tsg = gk20a_disable_tsg,
422 .tsg_verify_channel_status = gk20a_fifo_tsg_unbind_channel_verify_status,
423 .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload,
424 .reschedule_runlist = gk20a_fifo_reschedule_runlist,
425 .update_runlist = gk20a_fifo_update_runlist,
426 .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault,
427 .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info,
428 .wait_engine_idle = gk20a_fifo_wait_engine_idle,
429 .get_num_fifos = gm20b_fifo_get_num_fifos,
430 .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
431 .set_runlist_interleave = gk20a_fifo_set_runlist_interleave,
432 .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
433 .force_reset_ch = gk20a_fifo_force_reset_ch,
434 .engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
435 .device_info_data_parse = gp10b_device_info_data_parse,
436 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
437 .init_engine_info = gk20a_fifo_init_engine_info,
438 .runlist_entry_size = ram_rl_entry_size_v,
439 .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
440 .get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
441 .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc,
442 .dump_pbdma_status = gk20a_dump_pbdma_status,
443 .dump_eng_status = gk20a_dump_eng_status,
444 .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
445 .intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
446 .is_preempt_pending = gk20a_fifo_is_preempt_pending,
447 .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs,
448 .reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
449 .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
450 .handle_sched_error = gk20a_fifo_handle_sched_error,
451 .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0,
452 .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
453 .tsg_bind_channel = gk20a_tsg_bind_channel,
454 .tsg_unbind_channel = gk20a_tsg_unbind_channel,
455#ifdef CONFIG_TEGRA_GK20A_NVHOST
456 .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
457 .free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
458 .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
459 .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
460 .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
461 .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
462#endif
463 .resetup_ramfc = gp10b_fifo_resetup_ramfc,
464 .device_info_fault_id = top_device_info_data_fault_id_enum_v,
465 },
466 .gr_ctx = {
467 .get_netlist_name = gr_gp10b_get_netlist_name,
468 .is_fw_defined = gr_gp10b_is_firmware_defined,
469 },
470#ifdef CONFIG_GK20A_CTXSW_TRACE
471 .fecs_trace = {
472 .alloc_user_buffer = gk20a_ctxsw_dev_ring_alloc,
473 .free_user_buffer = gk20a_ctxsw_dev_ring_free,
474 .mmap_user_buffer = gk20a_ctxsw_dev_mmap_buffer,
475 .init = gk20a_fecs_trace_init,
476 .deinit = gk20a_fecs_trace_deinit,
477 .enable = gk20a_fecs_trace_enable,
478 .disable = gk20a_fecs_trace_disable,
479 .is_enabled = gk20a_fecs_trace_is_enabled,
480 .reset = gk20a_fecs_trace_reset,
481 .flush = gp10b_fecs_trace_flush,
482 .poll = gk20a_fecs_trace_poll,
483 .bind_channel = gk20a_fecs_trace_bind_channel,
484 .unbind_channel = gk20a_fecs_trace_unbind_channel,
485 .max_entries = gk20a_gr_max_entries,
486 },
487#endif /* CONFIG_GK20A_CTXSW_TRACE */
488 .mm = {
489 .support_sparse = gm20b_mm_support_sparse,
490 .gmmu_map = gk20a_locked_gmmu_map,
491 .gmmu_unmap = gk20a_locked_gmmu_unmap,
492 .vm_bind_channel = gk20a_vm_bind_channel,
493 .fb_flush = gk20a_mm_fb_flush,
494 .l2_invalidate = gk20a_mm_l2_invalidate,
495 .l2_flush = gk20a_mm_l2_flush,
496 .cbc_clean = gk20a_mm_cbc_clean,
497 .set_big_page_size = gm20b_mm_set_big_page_size,
498 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
499 .get_default_big_page_size = gp10b_mm_get_default_big_page_size,
500 .gpu_phys_addr = gm20b_gpu_phys_addr,
501 .get_iommu_bit = gp10b_mm_get_iommu_bit,
502 .get_mmu_levels = gp10b_mm_get_mmu_levels,
503 .init_pdb = gp10b_mm_init_pdb,
504 .init_mm_setup_hw = gp10b_init_mm_setup_hw,
505 .is_bar1_supported = gm20b_mm_is_bar1_supported,
506 .alloc_inst_block = gk20a_alloc_inst_block,
507 .init_inst_block = gk20a_init_inst_block,
508 .mmu_fault_pending = gk20a_fifo_mmu_fault_pending,
509 .init_bar2_vm = gb10b_init_bar2_vm,
510 .init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup,
511 .remove_bar2_vm = gp10b_remove_bar2_vm,
512 .get_kind_invalid = gm20b_get_kind_invalid,
513 .get_kind_pitch = gm20b_get_kind_pitch,
514 },
515 .pramin = {
516 .enter = gk20a_pramin_enter,
517 .exit = gk20a_pramin_exit,
518 .data032_r = pram_data032_r,
519 },
520 .therm = {
521 .init_therm_setup_hw = gp10b_init_therm_setup_hw,
522 .elcg_init_idle_filters = gp10b_elcg_init_idle_filters,
523 },
524 .pmu = {
525 .pmu_setup_elpg = gp10b_pmu_setup_elpg,
526 .pmu_get_queue_head = pwr_pmu_queue_head_r,
527 .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
528 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
529 .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
530 .pmu_queue_head = gk20a_pmu_queue_head,
531 .pmu_queue_tail = gk20a_pmu_queue_tail,
532 .pmu_msgq_tail = gk20a_pmu_msgq_tail,
533 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
534 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
535 .pmu_mutex_release = gk20a_pmu_mutex_release,
536 .write_dmatrfbase = gp10b_write_dmatrfbase,
537 .pmu_elpg_statistics = gp10b_pmu_elpg_statistics,
538 .pmu_pg_init_param = gp10b_pg_gr_init,
539 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
540 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
541 .dump_secure_fuses = pmu_dump_security_fuses_gp10b,
542 .reset_engine = gk20a_pmu_engine_reset,
543 .is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
544 },
545 .regops = {
546 .get_global_whitelist_ranges =
547 gp10b_get_global_whitelist_ranges,
548 .get_global_whitelist_ranges_count =
549 gp10b_get_global_whitelist_ranges_count,
550 .get_context_whitelist_ranges =
551 gp10b_get_context_whitelist_ranges,
552 .get_context_whitelist_ranges_count =
553 gp10b_get_context_whitelist_ranges_count,
554 .get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist,
555 .get_runcontrol_whitelist_count =
556 gp10b_get_runcontrol_whitelist_count,
557 .get_runcontrol_whitelist_ranges =
558 gp10b_get_runcontrol_whitelist_ranges,
559 .get_runcontrol_whitelist_ranges_count =
560 gp10b_get_runcontrol_whitelist_ranges_count,
561 .get_qctl_whitelist = gp10b_get_qctl_whitelist,
562 .get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count,
563 .get_qctl_whitelist_ranges = gp10b_get_qctl_whitelist_ranges,
564 .get_qctl_whitelist_ranges_count =
565 gp10b_get_qctl_whitelist_ranges_count,
566 .apply_smpc_war = gp10b_apply_smpc_war,
567 },
568 .mc = {
569 .intr_enable = mc_gp10b_intr_enable,
570 .intr_unit_config = mc_gp10b_intr_unit_config,
571 .isr_stall = mc_gp10b_isr_stall,
572 .intr_stall = mc_gp10b_intr_stall,
573 .intr_stall_pause = mc_gp10b_intr_stall_pause,
574 .intr_stall_resume = mc_gp10b_intr_stall_resume,
575 .intr_nonstall = mc_gp10b_intr_nonstall,
576 .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
577 .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
578 .enable = gk20a_mc_enable,
579 .disable = gk20a_mc_disable,
580 .reset = gk20a_mc_reset,
581 .boot_0 = gk20a_mc_boot_0,
582 .is_intr1_pending = mc_gp10b_is_intr1_pending,
583 },
584 .debug = {
585 .show_dump = gk20a_debug_show_dump,
586 },
587 .dbg_session_ops = {
588 .exec_reg_ops = exec_regops_gk20a,
589 .dbg_set_powergate = dbg_set_powergate,
590 .check_and_set_global_reservation =
591 nvgpu_check_and_set_global_reservation,
592 .check_and_set_context_reservation =
593 nvgpu_check_and_set_context_reservation,
594 .release_profiler_reservation =
595 nvgpu_release_profiler_reservation,
596 .perfbuffer_enable = gk20a_perfbuf_enable_locked,
597 .perfbuffer_disable = gk20a_perfbuf_disable_locked,
598 },
599 .bus = {
600 .init_hw = gk20a_bus_init_hw,
601 .isr = gk20a_bus_isr,
602 .read_ptimer = gk20a_read_ptimer,
603 .get_timestamps_zipper = nvgpu_get_timestamps_zipper,
604 .bar1_bind = gk20a_bus_bar1_bind,
605 },
606#if defined(CONFIG_GK20A_CYCLE_STATS)
607 .css = {
608 .enable_snapshot = css_hw_enable_snapshot,
609 .disable_snapshot = css_hw_disable_snapshot,
610 .check_data_available = css_hw_check_data_available,
611 .set_handled_snapshots = css_hw_set_handled_snapshots,
612 .allocate_perfmon_ids = css_gr_allocate_perfmon_ids,
613 .release_perfmon_ids = css_gr_release_perfmon_ids,
614 },
615#endif
616 .falcon = {
617 .falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
618 },
619 .priv_ring = {
620 .isr = gp10b_priv_ring_isr,
621 },
622 .chip_init_gpu_characteristics = gp10b_init_gpu_characteristics,
623 .get_litter_value = gp10b_get_litter_value,
624};
625
626int gp10b_init_hal(struct gk20a *g)
627{
628 struct gpu_ops *gops = &g->ops;
629 u32 val;
630
631 gops->ltc = gp10b_ops.ltc;
632 gops->ce2 = gp10b_ops.ce2;
633 gops->gr = gp10b_ops.gr;
634 gops->fb = gp10b_ops.fb;
635 gops->clock_gating = gp10b_ops.clock_gating;
636 gops->fifo = gp10b_ops.fifo;
637 gops->gr_ctx = gp10b_ops.gr_ctx;
638#ifdef CONFIG_GK20A_CTXSW_TRACE
639 gops->fecs_trace = gp10b_ops.fecs_trace;
640#endif
641 gops->mm = gp10b_ops.mm;
642 gops->pramin = gp10b_ops.pramin;
643 gops->therm = gp10b_ops.therm;
644 gops->pmu = gp10b_ops.pmu;
645 gops->regops = gp10b_ops.regops;
646 gops->mc = gp10b_ops.mc;
647 gops->debug = gp10b_ops.debug;
648 gops->dbg_session_ops = gp10b_ops.dbg_session_ops;
649 gops->bus = gp10b_ops.bus;
650#if defined(CONFIG_GK20A_CYCLE_STATS)
651 gops->css = gp10b_ops.css;
652#endif
653 gops->falcon = gp10b_ops.falcon;
654
655 gops->priv_ring = gp10b_ops.priv_ring;
656
657 /* Lone Functions */
658 gops->chip_init_gpu_characteristics =
659 gp10b_ops.chip_init_gpu_characteristics;
660 gops->get_litter_value = gp10b_ops.get_litter_value;
661
662 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
663 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
664
665#ifdef CONFIG_TEGRA_ACR
666 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
667 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
668 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
669 } else if (g->is_virtual) {
670 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
671 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
672 } else {
673 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
674 if (val) {
675 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
676 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
677 } else {
678 gk20a_dbg_info("priv security is disabled in HW");
679 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
680 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
681 }
682 }
683#else
684 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
685 gk20a_dbg_info("running simulator with PRIV security disabled");
686 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
687 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
688 } else {
689 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
690 if (val) {
691 gk20a_dbg_info("priv security is not supported but enabled");
692 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
693 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
694 return -EPERM;
695 } else {
696 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
697 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
698 }
699 }
700#endif
701
702 /* priv security dependent ops */
703 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
704 /* Add in ops from gm20b acr */
705 gops->pmu.is_pmu_supported = gm20b_is_pmu_supported,
706 gops->pmu.prepare_ucode = prepare_ucode_blob,
707 gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn,
708 gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap,
709 gops->pmu.is_priv_load = gm20b_is_priv_load,
710 gops->pmu.get_wpr = gm20b_wpr_info,
711 gops->pmu.alloc_blob_space = gm20b_alloc_blob_space,
712 gops->pmu.pmu_populate_loader_cfg =
713 gm20b_pmu_populate_loader_cfg,
714 gops->pmu.flcn_populate_bl_dmem_desc =
715 gm20b_flcn_populate_bl_dmem_desc,
716 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt,
717 gops->pmu.falcon_clear_halt_interrupt_status =
718 clear_halt_interrupt_status,
719 gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1,
720
721 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
722 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
723 gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap;
724 gops->pmu.is_priv_load = gp10b_is_priv_load;
725
726 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
727 } else {
728 /* Inherit from gk20a */
729 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported,
730 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
731 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1,
732 gops->pmu.pmu_nsbootstrap = pmu_bootstrap,
733
734 gops->pmu.load_lsfalcon_ucode = NULL;
735 gops->pmu.init_wpr_region = NULL;
736 gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1;
737
738 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
739 }
740
741 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
742 g->pmu_lsf_pmu_wpr_init_done = 0;
743 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
744
745 g->name = "gp10b";
746
747 return 0;
748}
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-22 13:38:48 -0400