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path: root/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c27
1 files changed, 9 insertions, 18 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 0b2a5712..335eb465 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -64,6 +64,7 @@
64 64
65#include "gp10b.h" 65#include "gp10b.h"
66#include "hal_gp10b.h" 66#include "hal_gp10b.h"
67#include "fuse_gp10b.h"
67 68
68#include <nvgpu/debug.h> 69#include <nvgpu/debug.h>
69#include <nvgpu/bug.h> 70#include <nvgpu/bug.h>
@@ -619,6 +620,9 @@ static const struct gpu_ops gp10b_ops = {
619 .priv_ring = { 620 .priv_ring = {
620 .isr = gp10b_priv_ring_isr, 621 .isr = gp10b_priv_ring_isr,
621 }, 622 },
623 .fuse = {
624 .check_priv_security = gp10b_fuse_check_priv_security,
625 },
622 .chip_init_gpu_characteristics = gp10b_init_gpu_characteristics, 626 .chip_init_gpu_characteristics = gp10b_init_gpu_characteristics,
623 .get_litter_value = gp10b_get_litter_value, 627 .get_litter_value = gp10b_get_litter_value,
624}; 628};
@@ -626,7 +630,6 @@ static const struct gpu_ops gp10b_ops = {
626int gp10b_init_hal(struct gk20a *g) 630int gp10b_init_hal(struct gk20a *g)
627{ 631{
628 struct gpu_ops *gops = &g->ops; 632 struct gpu_ops *gops = &g->ops;
629 u32 val;
630 633
631 gops->ltc = gp10b_ops.ltc; 634 gops->ltc = gp10b_ops.ltc;
632 gops->ce2 = gp10b_ops.ce2; 635 gops->ce2 = gp10b_ops.ce2;
@@ -654,6 +657,8 @@ int gp10b_init_hal(struct gk20a *g)
654 657
655 gops->priv_ring = gp10b_ops.priv_ring; 658 gops->priv_ring = gp10b_ops.priv_ring;
656 659
660 gops->fuse = gp10b_ops.fuse;
661
657 /* Lone Functions */ 662 /* Lone Functions */
658 gops->chip_init_gpu_characteristics = 663 gops->chip_init_gpu_characteristics =
659 gp10b_ops.chip_init_gpu_characteristics; 664 gp10b_ops.chip_init_gpu_characteristics;
@@ -662,23 +667,9 @@ int gp10b_init_hal(struct gk20a *g)
662 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); 667 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
663 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); 668 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
664 669
665 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { 670 /* Read fuses to check if gpu needs to boot in secure/non-secure mode */
666 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); 671 if (gops->fuse.check_priv_security(g))
667 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); 672 return -EINVAL; /* Do not boot gpu */
668 } else if (g->is_virtual) {
669 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
670 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
671 } else {
672 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
673 if (val) {
674 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
675 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
676 } else {
677 gk20a_dbg_info("priv security is disabled in HW");
678 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
679 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
680 }
681 }
682 673
683 /* priv security dependent ops */ 674 /* priv security dependent ops */
684 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { 675 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {